ZetaGig provides purpose‑built SHA‑256 ASICs for Bitcoin mining, delivering 175–325 GH/s at 3.8–8 W, which translates to 19.5–27 J/TH energy efficiency. The 2‑billion‑transistor Z1 chip integrates 676 parallel engines and on‑die power‑regulation to reduce dynamic power loss, and is offered as silicon‑ready IP for miner OEMs. Future roadmap targets a 2 nm node with sub‑6 J/TH performance.
Funding
Funding not disclosed
Founders
Product
Problem
Bitcoin mining relies on high‑performance ASICs that consume large amounts of electricity, driving up operational costs and limiting the scalability of mining operations. Existing chips often trade off hash rate for energy efficiency, creating a barrier for miners seeking sustainable, cost‑effective hardware.
Solution
ZetaGig engineers purpose‑built ASICs optimized for SHA‑256 mining, leveraging proprietary pipelining techniques and custom digital circuit designs to maximize hash throughput while minimizing joules per terahash. The Z1 chip integrates 676 SHA‑256 engines within a 2‑billion‑transistor die, delivering 175–325 GH/s at an measured power envelope of 3.8–8 W, which translates to 21.8–27 J/TH in a pre‑production process and an expected 19.5–24.5 J/TH in a production PDK. Advanced clock‑distribution and on‑chip power‑regulation architectures further reduce silicon area and dynamic power loss. ZetaGig’s roadmap targets a 2 nm node capable of sub‑6 J/TH performance, positioning its ASICs as the most energy‑efficient solution for next‑generation Bitcoin mining farms. All designs are delivered as silicon‑ready IP, enabling rapid integration into miner manufacturers’ hardware platforms.
Target Audience
The primary customers are large‑scale Bitcoin mining operators and OEMs that build dedicated mining rigs, who require ultra‑efficient, high‑throughput ASICs to lower electricity costs and increase profitability.
Features
- 2 billion‑transistor ASIC with 676 parallel SHA‑256 engines for high parallelism
- Optimized SHA‑256 pipeline architecture delivering 175–325 GH/s per chip
- Integrated on‑die clock‑distribution network and adaptive power‑regulation blocks to minimize dynamic power consumption
- Measured power draw of 3.8–8 W, achieving 21.8–27 J/TH (pre‑production) and projected 19.5–24.5 J/TH (production)
- Silicon‑area efficiency gains from custom digital macro cells and reduced gate count
- Compatibility with major foundry PDKs; tape‑out completed on pre‑production node, with a 2 nm production roadmap targeting <6 J/TH
- Full IP delivery package includes RTL, layout, verification suite, and integration guidelines for OEM miner designs