zapRF

ZapRF automates the design and optimization of power amplifier chips, reducing the design process from months to hours. Their platform delivers tapeout-ready designs, accelerating chip development for power amplifiers.

Austin, United States

Updated 2 months ago

Funding

Funding not disclosed

Funding rounds are not available yet.

Founders

Founder details are not available yet.

Product

Problem

Designing radio frequency (RF) power amplifier (PA) chips is a complex and time-consuming process, often taking months due to iterative manual design, simulation, and layout adjustments. This lengthy design cycle increases engineering and licensing costs and delays time to market for new products.

Solution

ZapRF offers an automated platform that significantly accelerates the design and optimization of RF PA chips, reducing the design cycle from months to hours. The platform uses advanced algorithms and machine learning to automate topology selection, component sizing, simulation, and layout, delivering tapeout-ready designs. By orchestrating every major RFIC/MMIC design step in a single, integrated flow, ZapRF removes repetitive tasks and minimizes human error. The platform's rule engine ingests multiple PDKs and enforces design rule checking (DRC) and layout versus schematic (LVS) constraints automatically, enabling designers to target different processes without retooling.

Target Audience

The primary target audience includes RFIC and MMIC designers and engineering teams looking to accelerate the development of power amplifier chips and reduce associated costs.

Features

End-to-end workflow automation orchestrates every major RFIC/MMIC design step in a single, integrated flow.
PDK-agnostic DRC/LVS-compliant layout enables designers to target different processes without retooling.
AI-powered topology selection and component sizing automatically evaluates specification requirements, sifts through topology libraries, and determines bias for best performance.
Closed-loop simulation and optimization embeds fast-path EM extraction and performance feedback into its AI agents, automatically refining designs until spec compliance is achieved.
One-click GDS-II output for a streamlined tapeout process.
Built-in human-in-the-loop checkpoints for bias and impedance review.
Seamless toolchain integration.
Correct-by-construction layouts auto-repair any DRC or LVS violations on the fly.