Yorchip provides end‑to‑end custom ASIC design services, offering a library of licensed mixed‑signal and digital IP cores optimized for low power and high performance. The flow includes specification capture, RTL synthesis, automated place‑and‑route, verification, tape‑out, and silicon bring‑up, with flexible licensing for reuse across projects. It targets semiconductor OEMs and system integrators needing custom silicon for IoT, automotive, aerospace, and industrial applications.
Funding
Funding not disclosed
Founders
Product
Problem
Designing high‑performance integrated circuits for niche digital or mixed‑signal applications often requires extensive engineering effort, long development cycles, and expensive off‑the‑shelf components that cannot meet strict power‑budget or latency constraints.
Solution
Yorchip delivers end‑to‑end custom ASIC design services combined with a catalog of licensed IP cores tailored for complex digital and mixed‑signal workloads. The company leverages advanced RTL synthesis, place‑and‑route automation, and silicon‑proven standard‑cell libraries to achieve higher clock speeds while minimizing power draw. Its mixed‑signal expertise integrates high‑precision analog front‑ends with digital logic on a single die, reducing board count and BOM cost. Yorchip’s design flow includes full verification, timing closure, and post‑silicon validation, ensuring that tape‑out timelines align with customer product roadmaps. Clients receive a flexible IP licensing model that allows reuse across multiple projects, accelerating time‑to‑market. All deliverables are packaged with comprehensive documentation and API hooks for seamless integration into existing hardware‑software stacks.
Target Audience
Primary customers are semiconductor OEMs, system‑level integrators, and specialty device manufacturers in sectors such as IoT, automotive, aerospace, and industrial automation that require custom silicon to meet performance‑power trade‑offs.
Features
- Full‑stack ASIC design service from specification capture through tape‑out and silicon bring‑up
- Proprietary mixed‑signal IP library (ADCs, DACs, PLLs, sensor interfaces) optimized for low‑power operation
- High‑performance digital IP blocks (cryptographic engines, AI accelerators, high‑speed serializers) with configurable datapaths
- Silicon‑proven standard‑cell and analog macro libraries supporting sub‑100 nm process nodes
- Automated design‑for‑manufacturability checks (DFM, yield‑aware placement, voltage‑stack analysis)
- Integrated verification suite (UVM testbenches, formal equivalence checking, power‑analysis tools)
- Flexible licensing options (per‑project, perpetual, or subscription) with source‑code access for rapid IP reuse
- API‑ready design data (EDIF, GDSII, JEDEC) and compatibility with major EDA toolchains (Cadence, Synopsys, Mentor)