Xcelsa Labs
Xcelsa provides Verified Compute Intelligence, a platform that combines formal equivalence checking with AI-powered physical world models to accelerate chip design optimization. Its Apex product automatically optimizes RTL for power, performance, and area while preserving behavioral equivalence, achieving 1,000× faster equivalence checking and 100× fewer EDA tool calls compared to existing workflows.
- Semiconductor
- Artificial Intelligence
- Software Only
Funding
Founders
Founder details are not available yet.
Product
Problem
Chip design teams face slow verification cycles and limited design exploration because formal equivalence checking and physical feedback from electronic design automation (EDA) tools are computationally expensive. This forces engineers to choose between thorough verification and exploring more design alternatives, delaying time to market and constraining silicon performance.
Solution
Xcelsa provides Verified Compute Intelligence, a platform that combines a verified intelligence stack with a physical intelligence stack to optimize chip designs faster. The verified stack formally proves that each candidate design is equivalent to the reference design, while the physical stack uses world models to predict power, performance, and area outcomes without running full EDA tool simulators. This enables designers to evaluate more alternatives and focus expensive EDA runs only on promising candidates, resulting in optimized RTL that is formally equivalent to the original design. The platform's product, Apex, automates design optimization while preserving behavioral equivalence.
Target Audience
Primary customers are semiconductor design teams and chip companies that need faster design optimization and verification, including those working on advanced digital and analog integrated circuits.
Features
- Apex AI system that automatically optimizes RTL for power, performance, and area while preserving behavioral equivalence
- Verified intelligence stack with 1,000× faster equivalence checking compared with existing workflows
- Physical intelligence stack using world models to reason through physical outcomes, reducing EDA tool calls by 100×
- Open-source research contributions including Lea (Lean 4 theorem-proving agent), VeriThoughts (Verilog generation with formal verification), ABC-RL (reinforcement learning for logic synthesis), and Masala-CHAI (analog schematic-to-SPICE translation tools)