Visionchip

Visionchip provides custom ASIC and semiconductor IP that integrates image‑signal processing, on‑chip memory, and AI inference engines to accelerate vision pipelines on edge devices. The chips deliver sub‑microsecond latency for 1080p‑60 fps and 4K‑30 fps video with >80 TOPS/W, and are supported by an SDK that maps TensorFlow Lite, ONNX, and OpenCV workloads. Targeted at OEMs and system integrators building smart cameras, industrial robots, and autonomous‑vehicle vision systems.

Updated 2 months ago

Funding

Funding not disclosed

Funding rounds are not available yet.

Founders

Founder details are not available yet.

Product

Problem

Many embedded vision systems rely on general‑purpose processors or legacy image‑signal processors that cannot meet the low‑latency, high‑throughput demands of modern machine‑vision and AI‑driven applications. The resulting bottlenecks limit frame rates, increase power consumption, and impede real‑time decision making in industrial automation and edge devices.

Solution

Visionchip delivers purpose‑built semiconductor IP and ASICs that accelerate image acquisition, preprocessing, and inference within a single silicon package. The chips implement a tightly coupled pipeline that minimizes data movement, delivering sub‑microsecond latency from sensor input to processed output. By integrating dedicated convolution engines, on‑chip memory hierarchies, and programmable logic, Visionchip enables deterministic performance for high‑resolution video streams at 60 fps and beyond. The architecture is optimized for low power envelope, making it suitable for battery‑operated or thermally constrained edge platforms. A comprehensive SDK and hardware abstraction layer allow OEMs to map existing computer‑vision frameworks directly onto the silicon, reducing development cycles. Visionchip also offers flexible packaging options, from bare die to system‑in‑package (SiP), to fit diverse form‑factor constraints in embedded systems.

Features

Custom ASIC with integrated image‑signal processing (ISP) front‑end and AI inference engines
Sub‑microsecond end‑to‑end latency for 1080p‑60 fps and 4K‑30 fps video pipelines
On‑chip high‑bandwidth memory (HBM/LPDDR) and DMA engines to eliminate off‑chip bottlenecks
Power‑aware design delivering >80 TOPS/W for convolutional workloads
MIPI‑CSI‑2, LVDS, and Ethernet interfaces with programmable I/O for sensor flexibility
SDK with C/C++ and Python bindings, supporting TensorFlow Lite, ONNX, and OpenCV integration
Optional FPGA fabric for customer‑specific post‑processing or protocol adaptation
SiP and BGA packaging options for space‑constrained edge modules