CEO and co-founder
Since Jul 2024 · 2 yrs 4 mos
Profile summary: Google
VerticalCompute
Vertical Compute develops a new class of semiconductor chiplets that integrate vertical columns of magnetic memory directly above processing cores, eliminating the data bus bottleneck that limits AI performance. The technology combines nano-magnetism with standard CMOS manufacturing to deliver DRAM-scale density with SRAM-like latency, enabling large language model inference on a single chip. This in-memory compute architecture targets enterprises, research institutions, and semiconductor partners seeking energy-efficient AI acceleration.
- Artificial Intelligence
- Hardware
- Semiconductor
Updated 2 months ago
Funding
Raised to date
€57MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Est. $62.1Macross 2 rounds
+7€37M · Seed Follow-On
Announced Mar 2026
Disclosed cumulative: $62.1M
2/2
RoundDateAmountValuationInvestors
Founders
Product
Problem
AI workloads, particularly large language models, require continuous data transfers between separate memory and compute chips—billions of times per second. This creates a "memory wall" bottleneck that limits performance, increases energy consumption, and prevents efficient on-chip inference for models that are too large to fit in conventional memory.
Solution
Vertical Compute creates a new compute paradigm by integrating vertical columns of magnetic data storage directly above processing cores on the same chip. The technology leverages the third dimension to place magnetic bit strings vertically in the transistor back-end, eliminating the data bus entirely. This architecture achieves greater than DRAM data density (over Gb/mm²) while maintaining nanosecond-scale SRAM-like access latency. By combining vertical memory with high-performance transistors, the platform enables energy-efficient in-memory computing capable of running LLM inference on a single chip. The approach is manufacturable by standard semiconductor foundries, allowing seamless integration into existing supply chains.
Target Audience
Primary customers include AI-driven enterprises needing scalable compute, advanced research institutions exploring high-performance computing, semiconductor foundries and memory chip vendors seeking next-gen architectures, and AI hardware and cloud providers optimizing data center efficiency.
Features
- Vertical magnetic bit strings integrated directly above transistors in the CMOS back-end, eliminating the data bus and its associated bandwidth bottleneck
- Data density exceeding 1 Gb/mm² with approximately 10ns access latency, combining DRAM-scale capacity with SRAM-like speed
- Direct CMOS integration in standard semiconductor processes, enabling production by existing foundries without specialized equipment
- Sub-picojoule per bit energy consumption with unlimited endurance for sustained AI workloads
- Single-chip architecture capable of LLM inference processing, supporting Gen AI, Agentic AI, and Physical AI applications
- Available for deployment both on-device and in cloud environments