Verilock delivers chip‑level security by leveraging chaos‑based cryptographic primitives to generate high‑entropy keys and authentication data directly within hardware. The solution enables tamper‑resistant key storage and secure boot for embedded and IoT devices, providing a lightweight yet robust protection mechanism without requiring external security modules.
Funding
Funding not disclosed
Founders
Product
Problem
Integrated circuits are vulnerable to tampering, reverse engineering, and side‑channel attacks, which can expose proprietary designs and confidential data. Semiconductor manufacturers often lack low‑overhead, hardware‑level protection that can be integrated into existing design flows.
Solution
Verilock provides a hardware security platform that embeds chaos‑based cryptographic primitives directly into silicon. By generating chip‑level keys and data that are intrinsically unpredictable, the solution makes it difficult for attackers to extract or manipulate sensitive IP. The approach adds minimal area and power overhead, allowing manufacturers to protect designs without compromising performance or cost. Verilock’s technology can be incorporated during standard ASIC or FPGA design processes, delivering built‑in resistance to tampering, reverse engineering, and side‑channel analysis.
Target Audience
Primary customers are semiconductor manufacturers and design houses that need to secure proprietary IP in ASICs, SoCs, and FPGA-based products.
Features
- Chaos‑driven key generation that produces non‑deterministic, high‑entropy secrets on-chip
- Low‑power, low‑area implementation suitable for a wide range of semiconductor processes
- Built‑in protection against side‑channel attacks such as power analysis and electromagnetic probing
- Compatibility with standard design toolchains for seamless integration into ASIC and FPGA flows
- Configurable security policies that can be tailored to specific IP protection requirements