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Veevx

Veevx is a fabless semiconductor company that designs ultra‑low power AI accelerator chips delivering data‑center‑class inference performance at roughly one‑tenth the typical power consumption. Their solutions integrate advanced power‑management techniques and provide reference designs and IP blocks, enabling smartphone, wearable, and IoT manufacturers to embed continuous on‑device AI while extending battery runtime two to three times.

Mesa, United StatesFounded 202215200+ followers
Updated 2 months ago

Funding

Funding not disclosed

Funding rounds are not available yet.

Founders

Founder details are not available yet.

Product

Problem

Mobile and edge devices require AI capabilities but are constrained by limited battery capacity, making it difficult to run compute-intensive models without frequent recharging or reduced functionality.

Solution

Veevx designs fabless semiconductor chips that deliver data‑center‑class AI inference performance while consuming roughly one‑tenth the power of comparable solutions. By optimizing architecture for ultra‑low power operation, the chips enable AI features such as vision, speech, and sensor processing to run continuously on battery‑powered devices, extending runtime by two to three times. The technology integrates standard AI accelerators with power‑saving techniques like voltage scaling, clock gating, and specialized low‑leakage transistors, allowing manufacturers to embed advanced AI without redesigning the entire system‑on‑chip. Veevx provides reference designs and IP packages that can be incorporated into smartphones, wearables, IoT sensors, and other edge products, facilitating faster time‑to‑market for AI‑enabled hardware.

Target Audience

Primary customers are semiconductor OEMs and device manufacturers developing smartphones, wearables, IoT sensors, and other battery‑operated edge products that require on‑device AI processing.

Features

  • Ultra‑low power AI accelerator delivering data‑center performance at ~10 % of typical power consumption
  • Integrated power‑management techniques (dynamic voltage/frequency scaling, clock gating, low‑leakage transistors)
  • Support for common AI frameworks and model formats via on‑chip inference engine
  • Reference design kits and IP blocks for easy integration into mobile, wearable, and IoT silicon
  • Scalable architecture that can be customized for different performance‑power trade‑offs
This profile is AI-generated and may contain inaccuracies.