ThinSiC develops ultra‑thin, all‑epitaxial silicon‑carbide (SiC) power devices using a proprietary lateral‑epitaxy process that consumes only 1–3 µm of SiC per substrate and enables up to ten‑fold substrate reuse, cutting wafer‑related capital costs by about 80 %. The resulting devices support currents above 200 A, higher voltage ratings, and faster switching speeds, delivering higher power density, lower thermal losses, and lighter converters for AI data centers, electric vehicles, aerospace, industrial drives, and smart‑grid applications.
Funding
Funding not disclosed
Founders
Product
Problem
Power electronics based on conventional silicon or standard silicon‑carbide wafers suffer from high switching losses, limited current capability, bulky form factors, and expensive, low‑yield manufacturing, which restricts efficiency and scalability for high‑power applications such as AI data centers, electric vehicles, aerospace, industrial drives, and modern power grids.
Solution
ThinSiC provides ultra‑thin, all‑epitaxial silicon‑carbide (SiC) power devices built on a proprietary lateral‑epitaxy process. The process consumes only 1–3 µm of SiC per substrate and enables ten‑fold substrate reuse, cutting wafer‑related capital costs by roughly 80 % and eliminating back‑grinding steps. The resulting devices support currents above 200 A, higher voltage ratings, and switching frequencies that reduce on‑resistance (RDS(ON)) and thermal losses. Scalable to 8‑inch wafers and adaptable to GaN, ThinSiC’s technology delivers higher power density, lighter converters, and superior thermal performance for a wide range of high‑efficiency power‑conversion markets.
Target Audience
Primary customers are OEMs and system integrators developing power‑dense solutions for data‑center AI hardware, electric vehicles and rail, aerospace propulsion, industrial motor drives, and next‑generation smart grid infrastructure.
Features
- Lateral epitaxy growth yields low‑defect, high‑yield SiC layers for reliable high‑current operation (>200 A)
- Ultra‑thin wafer separation allows up to 10× substrate reuse, slashing material cost and waste
- Faster switching speeds and lower RDS(ON) reduce conversion losses by 20–30 % and enable higher voltage devices
- Thermal performance supports high‑current (>200 A) operation with minimal cooling requirements
- Compatible with 8‑inch wafer production and can be extended to GaN platforms for broader applicability
- Enables solid‑state transformer designs and compact converters for grid, AI, EV, aerospace, and industrial motor applications