Tendrils
Tendrils is building a new general-purpose processor architecture designed to scale to thousands of parallel cores, moving beyond sequential designs and shared mutable memory. The company pairs this hardware with Vine, an open-source linear-type programming language that compiles directly to interaction nets, enabling developers to write familiar code that maps to the parallel hardware. The architecture guarantees locality and inherent parallelism through a graph-based interaction net model, eliminating global synchronization bottlenecks.
- Developer Tools
- Hardware
- Semiconductor
Funding
Raised to date
$30MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
across 1 round
ACVEVF+3$30M · Undisclosed
Announced Nov 2026
Disclosed cumulative: $30M
Founders
Product
Problem
Current general-purpose processor architectures struggle to scale efficiently to thousands of cores due to limited parallelism, high communication overhead, and difficulty exploiting fine-grained locality. This hampers performance for workloads that could benefit from massive parallel execution.
Solution
Tendrils proposes a new default chip built on a general-purpose architecture derived from interaction nets, a graph-based model that guarantees locality, inherent parallelism, and linear resource usage. By decomposing interaction nets into paired trees, the hardware can store and access active computation pairs directly, enabling massive parallel execution without costly global coordination. The company provides a linear-type programming language, Vine, that compiles directly to interaction nets, allowing developers to write familiar code while the compiler maps it to the underlying parallel hardware. This combination delivers a scalable, high-throughput platform that can efficiently run a wide range of algorithms, from simple arithmetic to dynamic-programming problems, on thousands of cores.
Target Audience
Primary customers are semiconductor companies, hardware architects, and high-performance computing platforms seeking a scalable, parallel-friendly processor design, as well as software developers who need a language and hardware stack for fine-grained parallel workloads.
Features
- Interaction-net based architecture where each computation step modifies only a local graph fragment, eliminating global synchronization bottlenecks
- Automatic exposure of all independent active pairs, allowing the hardware to execute them in parallel without programmer intervention
- Tree-based representation of interaction nets that provides constant-time access to active pairs and efficient memory layout
- Linear type system support via the Vine language, enabling safe compilation of high-level code to the interaction-net hardware model
- Built-in mechanisms for erasing and duplicating data that preserve linearity, reducing resource contention and improving predictability
- Designed to scale to thousands of cores while maintaining deterministic execution semantics
- Open-source Vine language with an active standard library development effort
- Hardware implementation spans architectural modeling in Rust, RTL design in SystemVerilog, and FPGA prototyping