Edge AI workloads on embedded devices are constrained by the memory‑compute bandwidth gap, where data must be shuttled between separate memory and processing units. This bottleneck inflates latency and power consumption, limiting the feasibility of advanced sensing and inference in wearables, robotics, and smart sensors. Synthara’s ComputeRAM™ embeds in‑memory computing (IMC) directly into standard embedded chips, allowing arithmetic operations to be performed where data resides.
Funding
Funding not disclosed
Founders
Product
Problem
Edge AI workloads on embedded devices are constrained by the memory‑compute bandwidth gap, where data must be shuttled between separate memory and processing units. This bottleneck inflates latency and power consumption, limiting the feasibility of advanced sensing and inference in wearables, robotics, and smart sensors.
Solution
Synthara’s ComputeRAM™ embeds in‑memory computing (IMC) directly into standard embedded chips, allowing arithmetic operations to be performed where data resides. By collapsing the memory‑compute interface, the solution delivers up to 100× higher throughput and comparable reductions in energy per operation without requiring additional silicon area or custom software stacks. The technology is delivered as a drop‑in IP block compatible with existing ASIC and SoC design flows, enabling chip makers to upgrade product performance instantly. ComputeRAM™ also provides a programmable API that lets OEMs map AI inference kernels—such as CNNs or lightweight LLMs—onto the in‑memory fabric, preserving flexibility while gaining deterministic low‑latency execution. All of this is packaged with a secure, end‑to‑end data path and industry‑standard verification suites to ensure reliability in safety‑critical edge applications.
Target Audience
Primary customers are semiconductor IP vendors, ASIC/SoC design teams, and OEMs developing edge AI products such as wearables, autonomous robots, and programmable smart sensors that require high‑performance, low‑power inference capabilities.
Features
- Drop‑in ComputeRAM™ IP core that integrates with standard CMOS process nodes and existing design toolchains (Cadence, Synopsys)
- Up to 100× speedup and 100× reduction in energy per operation for memory‑bound AI kernels
- In‑memory arithmetic engine supporting mixed‑precision (FP8/INT8) operations for CNNs, transformers, and signal‑processing workloads
- Programmable API and SDK for mapping custom inference graphs onto the IMC fabric without rewriting firmware
- Transparent integration with existing memory hierarchies (SRAM, eDRAM) and cache controllers, preserving existing memory maps
- Built‑in error‑correction and parity checks to meet automotive and medical safety standards (ISO‑26262, IEC‑60601)
- Secure data path with hardware‑rooted encryption for on‑chip data at rest and in transit
- Comprehensive verification suite (RTL simulation, formal checks, silicon‑proven test benches) for rapid IP qualification