Developing exciting new ways to print microelectronics
Syenta
Syenta provides a Localized Electrochemical Manufacturing (LEM) process that creates sub‑micron, wafer‑scale High‑Resolution Interconnects for chip‑to‑chip connections. By combining metal deposition and patterning in a single stamp‑based step, the technology delivers up to three times the throughput of conventional fabs and supports large‑area panels, enabling dramatically higher bandwidth between compute and memory for AI and high‑performance computing chips.
- Hardware
- Manufacturing / Industry 4.0
- Semiconductor
Updated 13 days ago
Funding
Raised to date
$5.7MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Funding rounds are not available yet.
Founders
Product
Problem
Current AI and high‑performance computing systems are limited by the bandwidth and density of chip‑to‑chip interconnects, which rely on conventional semiconductor packaging that cannot scale to sub‑micron resolutions or large wafer‑level integration. This creates a memory‑bandwidth bottleneck that hampers performance and increases manufacturing cost and complexity.
Solution
Syenta’s Localized Electrochemical Manufacturing (LEM) technology creates High‑Resolution Interconnects (HRIs) that enable sub‑micron, wafer‑scale chip‑to‑chip connections. By combining metal deposition and patterning in a single step using a stamp electrode with a dielectric pattern, LEM deposits metal precisely within defined electrochemical cells, eliminating the need for multiple lithography steps. The process supports large (>1000 mm²) panels and delivers three‑fold higher throughput than existing fab lines, allowing manufacturers to scale down interconnect dimensions, scale out to larger package sizes, and scale up production volume. This results in dramatically higher bandwidth between compute and memory, reducing the AI memory wall and enabling more efficient, high‑density system integration.
Target Audience
Primary customers are semiconductor manufacturers and fabless AI chip designers seeking to overcome memory‑bandwidth limits through advanced packaging, as well as system integrators building high‑performance compute modules for data centers and edge AI applications.
Features
- Single‑step deposition and patterning via stamp‑based electrochemical cells for micron‑scale metal placement
- Sub‑micron interconnect pitch (≤1 µm) delivering ultra‑high bandwidth connections
- Compatibility with large‑area panels (510–600 mm) and field sizes of 100–200 mm for wafer‑level integration
- Production throughput up to 3× that of conventional semiconductor fabs, supporting high‑volume manufacturing
- Enables wafer‑level system integration, reducing package count and interconnect length
- Designed for AI accelerators and high‑performance computing chips requiring dense compute‑memory interfaces