Syenta

About Syenta

Syenta provides a Localized Electrochemical Manufacturing (LEM) process that creates sub‑micron, wafer‑scale High‑Resolution Interconnects for chip‑to‑chip connections. By combining metal deposition and patterning in a single stamp‑based step, the technology delivers up to three times the throughput of conventional fabs and supports large‑area panels, enabling dramatically higher bandwidth between compute and memory for AI and high‑performance computing chips.

<problem>Current AI and high‑performance computing systems are limited by the bandwidth and density of chip‑to‑chip interconnects, which rely on conventional semiconductor packaging that cannot scale to sub‑micron resolutions or large wafer‑level integration. This creates a memory‑bandwidth bottleneck that hampers performance and increases manufacturing cost and complexity.</problem> <solution>Syenta’s Localized Electrochemical Manufacturing (LEM) technology creates High‑Resolution Interconnects (HRIs) that enable sub‑micron, wafer‑scale chip‑to‑chip connections. By combining metal deposition and patterning in a single step using a stamp electrode with a dielectric pattern, LEM deposits metal precisely within defined electrochemical cells, eliminating the need for multiple lithography steps. The process supports large (>1000 mm²) panels and delivers three‑fold higher throughput than existing fab lines, allowing manufacturers to scale down interconnect dimensions, scale out to larger package sizes, and scale up production volume. This results in dramatically higher bandwidth between compute and memory, reducing the AI memory wall and enabling more efficient, high‑density system integration.</solution> <features> - Single‑step deposition and patterning via stamp‑based electrochemical cells for micron‑scale metal placement - Sub‑micron interconnect pitch (≤1 µm) delivering ultra‑high bandwidth connections - Compatibility with large‑area panels (510–600 mm) and field sizes of 100–200 mm for wafer‑level integration - Production throughput up to 3× that of conventional semiconductor fabs, supporting high‑volume manufacturing - Enables wafer‑level system integration, reducing package count and interconnect length - Designed for AI accelerators and high‑performance computing chips requiring dense compute‑memory interfaces </features> <target_audience>Primary customers are semiconductor manufacturers and fabless AI chip designers seeking to overcome memory‑bandwidth limits through advanced packaging, as well as system integrators building high‑performance compute modules for data centers and edge AI applications.</target_audience>

What does Syenta do?

Syenta provides a Localized Electrochemical Manufacturing (LEM) process that creates sub‑micron, wafer‑scale High‑Resolution Interconnects for chip‑to‑chip connections. By combining metal deposition and patterning in a single stamp‑based step, the technology delivers up to three times the throughput of conventional fabs and supports large‑area panels, enabling dramatically higher bandwidth between compute and memory for AI and high‑performance computing chips.

Where is Syenta located?

Syenta is based in Sydney, Australia.

When was Syenta founded?

Syenta was founded in 2022.

How much funding has Syenta raised?

Syenta has raised $5.7M.

Location
Sydney, Australia
Founded
2022
Funding
$5.7M
Employees
49 employees
Investors
InvestibleBlackbirdSalus
S

Syenta

Syenta provides a Localized Electrochemical Manufacturing (LEM) process that creates sub‑micron, wafer‑scale High‑Resolution Interconnects for chip‑to‑chip connections. By combining metal deposition and patterning in a single stamp‑based step, the technology delivers up to three times the throughput of conventional fabs and supports large‑area panels, enabling dramatically higher bandwidth between compute and memory for AI and high‑performance computing chips.

Sydney, AustraliaFounded 2022505K+ followers10/10 TractionRelative Traction Score based on online presence metrics compared to companies in the same age group.
Updated 2 months ago

Funding

$5.7M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.

7O
Funding rounds are not available yet.

Founders

Product

Problem

Current semiconductor packaging methods struggle to provide the sub‑micron, high‑density interconnects needed for wafer‑level system integration, limiting bandwidth between compute and memory and creating a bottleneck for AI and high‑performance computing workloads.

Solution

Syenta’s Localized Electrochemical Manufacturing (LEM) technology merges metal deposition and patterning into a single step using a stamp electrode with a dielectric pattern that creates localized electrochemical cells. This enables precise, sub‑micron metal placement across large (>1000 mm²) packages while delivering three times the throughput of conventional fabs. The resulting high‑resolution interconnects support ultra‑dense chip‑to‑chip connections, increasing bandwidth and allowing scalable wafer‑level integration. By offering “scale‑down,” “scale‑out,” and “scale‑up” capabilities, LEM provides a pathway to higher‑volume production of advanced packaging solutions that overcome the compute‑memory bandwidth barrier.

Target Audience

Primary customers are semiconductor manufacturers and fabless chip designers developing AI accelerators, high‑performance computing processors, and other advanced integrated circuits that require ultra‑dense, high‑bandwidth interconnects.

Features

  • Single‑step deposition and patterning via stamp‑based electrochemical cells for sub‑micron metal resolution
  • Capability to fabricate interconnects on large‑area packages (>1000 mm²) with panel sizes up to 600 mm
  • Three‑fold increase in manufacturing throughput compared with traditional semiconductor fabs
  • Scalable architecture supporting finer line‑widths (≤1 µm RDL), larger field sizes (100‑200 mm), and high‑volume production
  • Enables wafer‑level system integration, reducing the need for multiple packaging steps and improving overall device performance
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