Syenta provides a Localized Electrochemical Manufacturing (LEM) process that creates sub‑micron, wafer‑scale High‑Resolution Interconnects for chip‑to‑chip connections. By combining metal deposition and patterning in a single stamp‑based step, the technology delivers up to three times the throughput of conventional fabs and supports large‑area panels, enabling dramatically higher bandwidth between compute and memory for AI and high‑performance computing chips.
Funding
$5.7M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
- Startup funding source · Source unavailable
Founders
Product
Problem
Current semiconductor packaging methods struggle to provide the sub‑micron, high‑density interconnects needed for wafer‑level system integration, limiting bandwidth between compute and memory and creating a bottleneck for AI and high‑performance computing workloads.
Solution
Syenta’s Localized Electrochemical Manufacturing (LEM) technology merges metal deposition and patterning into a single step using a stamp electrode with a dielectric pattern that creates localized electrochemical cells. This enables precise, sub‑micron metal placement across large (>1000 mm²) packages while delivering three times the throughput of conventional fabs. The resulting high‑resolution interconnects support ultra‑dense chip‑to‑chip connections, increasing bandwidth and allowing scalable wafer‑level integration. By offering “scale‑down,” “scale‑out,” and “scale‑up” capabilities, LEM provides a pathway to higher‑volume production of advanced packaging solutions that overcome the compute‑memory bandwidth barrier.
Target Audience
Primary customers are semiconductor manufacturers and fabless chip designers developing AI accelerators, high‑performance computing processors, and other advanced integrated circuits that require ultra‑dense, high‑bandwidth interconnects.
Features
- Single‑step deposition and patterning via stamp‑based electrochemical cells for sub‑micron metal resolution
- Capability to fabricate interconnects on large‑area packages (>1000 mm²) with panel sizes up to 600 mm
- Three‑fold increase in manufacturing throughput compared with traditional semiconductor fabs
- Scalable architecture supporting finer line‑widths (≤1 µm RDL), larger field sizes (100‑200 mm), and high‑volume production
- Enables wafer‑level system integration, reducing the need for multiple packaging steps and improving overall device performance