Founder & CEO
Profile summary: MS in Economics at Stanford University
Spheresemi
Spheresemi provides an AI‑driven platform that automatically generates, evaluates, and optimizes custom RF and mixed‑signal semiconductor blocks, delivering production‑ready layouts that are DRC/LVS‑clean and PDK‑aware. Customers receive either fabricated chips or reusable IP—such as LNAs, PAs, filters, beamformers, SerDes, ADCs, and DACs—tailored to specific performance targets, often surpassing human‑only design baselines while reducing development time and cost.
- Artificial Intelligence
- Hardware
- Semiconductor
Updated 16 days ago
Funding
Raised to date
$20MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
across 2 rounds
+2$7.5M · Seed
Announced Sep 2025
Disclosed cumulative: $20M
2/2
RoundDateAmountValuationInvestors
Founders
Product
Problem
Designing high‑performance RF and mixed‑signal semiconductor blocks traditionally relies on manual layout and iterative prototyping, which is time‑consuming, costly, and limited by human intuition. This slows time‑to‑market for products that need custom analog components such as LNAs, PAs, filters, or high‑speed SerDes.
Solution
Spheresemi applies an AI‑driven design engine to generate, evaluate, and optimize analog and mixed‑signal circuit layouts automatically. The platform produces thousands of candidate designs in days, selects those that meet specified performance targets, and ensures they are DRC/LVS‑clean and manufacturable within the target PDK. Customers receive either a custom fabricated chip or reusable IP that matches their exact specifications, with performance that often exceeds human‑only baselines. By reducing manual design cycles, Spheresemi shortens development timelines and improves unit economics for specialized RF and mixed‑signal solutions.
Target Audience
Primary customers are semiconductor companies, hardware OEMs, and system integrators developing advanced wireless, radar, or high‑speed data‑link products that require bespoke RF or mixed‑signal blocks.
Features
- AI engine that generates and evaluates thousands of circuit layouts per design cycle, accelerating the exploration of the design space
- Automatic DRC/LVS verification and PDK awareness to deliver production‑ready, manufacturable layouts
- Custom RF components (LNAs, PAs, filters, phase shifters, beamformers, synthesizers) optimized for wideband, mmWave/sub‑THz, low noise, high PAE, and tight group delay requirements
- Tailored mixed‑signal IP blocks, including tunable SerDes lanes and ADC/DAC architectures (SAR, pipeline, sigma‑delta) configurable for area, speed, and power targets
- Performance‑focused optimization that can surpass human‑only design baselines, revealing non‑obvious circuit topologies
- End‑to‑end flow from AI‑generated schematic to fabricated silicon, enabling rapid delivery of custom chips or drop‑in IP