Artemis is an ultra‑low‑power ASIC accelerator that operates at near‑threshold voltage (≈0.275 V) and uses an asynchronous massively parallel architecture to deliver AI inference with about 35 % lower power consumption than comparable HPC accelerators. The platform integrates on‑chip ADCs, vector extensions, and a CXL‑compatible interconnect to enable near‑data processing and coherent memory access for hyperscale data‑center and edge AI workloads.
Funding
Funding not disclosed
Founders
Product
Problem
Data centers running AI and high‑performance computing (HPC) workloads face escalating power consumption and thermal constraints, which increase operating costs and carbon emissions. Existing ASIC accelerators often require high supply voltages and rely on synchronous designs that limit energy efficiency at scale.
Solution
Soteria’s Artemis platform delivers an ultra‑low‑power ASIC cloud accelerator that combines near‑threshold voltage operation (≈0.275 V) with an asynchronous massively parallel processing architecture. The device‑centric design integrates vector‑extension units for data pre‑processing, augmentation, and near‑data inference, reducing data movement between storage and compute. By embedding analog‑to‑digital hybrid converters and smart cache accelerators, Artemis achieves high‑throughput AI inference while keeping power draw 35 % below comparable HPC accelerators. The architecture is CXL‑enabled and supports scalable coherent memory access, making it compatible with immersion‑cooling systems and modern data‑center interconnects. A hardware‑software co‑design flow provides developers with optimized libraries and firmware to accelerate ML training pipelines without extensive custom integration.
Target Audience
Primary customers are hyperscale data‑center operators, cloud service providers, and HPC system integrators that run AI/ML training and inference workloads, as well as edge computing platforms seeking energy‑efficient AI acceleration.
Features
- Near‑threshold voltage (0.275 V) standard‑cell re‑characterization for sub‑50 mW/mm² power density
- Asynchronous massively parallel processing array (MPPA) with dynamic vector extensions for data augmentation and inference
- Integrated analog‑digital hybrid ADCs enabling on‑chip data conversion and near‑data processing (NDP)
- CXL‑compatible high‑speed interconnect and scalable coherent memory access for seamless CPU‑accelerator coupling
- Smart cache accelerator with prefetching and hardware‑managed data tiling to minimize memory bandwidth bottlenecks
- Immersion‑cooling‑ready layout and thermal‑aware floorplanning for exascale data‑center deployments
- Full hardware‑software co‑design toolchain, including firmware libraries and performance profiling utilities