SisuSemi provides an ultra‑high‑vacuum, sub‑450 °C ALP™ (Atomic Level Purification) process that removes hydrogen, carbon and other atomic impurities from silicon wafers and forms a 1 nm crystalline SiO₂ passivation layer. The service reduces defect density by up to 400 % and leakage current by 70 %, delivering up to 20 % yield improvement for IDM, foundry and fabless customers targeting sub‑3 nm CMOS nodes.
Funding
Funding not disclosed
Founders
Product
Problem
Atomic‑scale contaminants and interface defects on semiconductor wafers introduce trap states, increase leakage currents, and cause yield loss as device dimensions shrink to sub‑3 nm nodes. These imperfections degrade electrical performance, reliability, and power efficiency across a wide range of chip applications.
Solution
SisuSemi delivers its proprietary ALP™ (Atomic Level Purification) process, which combines ultra‑high‑vacuum (UHV) conditions, sub‑450 °C thermal treatment, and precisely controlled oxidation to remove hydrogen, carbon, and other atomic impurities from silicon surfaces. The treatment restores the crystalline order of the surface and grows an ultra‑thin, crystalline SiO₂ passivation layer that protects the interface during downstream processing. By eliminating atomic‑level defects, the process reduces defect density by 3–4× and cuts leakage current by up to 70%, translating into up to a 20 % yield lift and a 50 % extension of battery life in power‑constrained devices. The solution is offered through a staged engagement—feasibility testing, commercial piloting, and full‑scale implementation—allowing customers to validate performance gains before integration. All data are captured via TEM imaging and surface analytics, and the technology is protected by a global patent portfolio. Integration is designed to be retrofit‑friendly or greenfield, requiring minimal line downtime and no major equipment overhaul.
Target Audience
Primary customers are integrated device manufacturers (IDMs), semiconductor foundries, and fabless design houses developing high‑performance chips for mobile, IoT, data‑center, AI, and emerging quantum applications.
Features
- UHV‑based cleaning cycle with controlled O₂ flow at < 450 °C for atomic‑scale impurity removal
- Formation of a 1 nm crystalline SiO₂ interfacial layer that passivates the silicon surface
- Demonstrated 300–400 % reduction in defect density and up to 70 % leakage current suppression
- Compatibility with advanced nodes (3 nm and below) and standard CMOS process flows
- Modular service model: feasibility test, pilot integration, and commercial rollout with KPI‑driven reporting
- In‑line surface analysis (TEM, spectroscopy) and post‑process analytics dashboard for real‑time insight
- Extensive global patent portfolio securing IP and enabling exclusive commercial use