Simplex Micro provides a configurable RISC‑V processor IP that combines a time‑based scheduling architecture with a scalable vector engine, delivering GPU‑class throughput at lower power and silicon area. The design offers customizable vector register widths (128‑2048 bits) and extensible ISA extensions, enabling semiconductor and system‑integrator customers to embed deterministic, high‑performance edge AI compute directly into ASICs.
Funding
Funding not disclosed
Founders
Product
Problem
Edge AI and autonomous systems require high-performance compute for vector workloads, but traditional GPUs and TPUs consume excessive power and occupy large silicon area, making them unsuitable for power‑constrained or space‑limited devices.
Solution
Simplex Micro offers a configurable RISC‑V processor IP that combines a time‑based scheduling architecture with a scalable vector engine. By statically dispatching instructions based on a time counter, the design eliminates speculative execution overhead, delivering GPU‑class throughput with markedly lower power draw and silicon footprint. The processor supports customizable vector register widths from 128 bits up to 2048 bits, allowing designers to match compute density to application needs such as mobile AI, AR/VR, or data‑center inference. Native RISC‑V compatibility ensures seamless integration into existing toolchains and software ecosystems, while the modular ISA enables extensions for domain‑specific instructions. Licensed IP can be embedded directly into ASICs, providing deterministic performance per watt for real‑time edge processing and scalable inference workloads.
Target Audience
Primary customers are semiconductor companies and system‑integrators developing edge AI, autonomous platforms, industrial automation controllers, and high‑density inference accelerators that require efficient vector processing.
Features
- Time‑based scheduling (TBS) architecture that statically dispatches instructions, removing speculative execution and reducing wasted silicon
- Configurable vector register width (128‑2048 bits) for flexible performance scaling across diverse AI/ML workloads
- RISC‑V ISA compatibility with extensible custom instruction sets for application‑specific acceleration
- Compact silicon area and low power consumption compared to traditional GPU/TPU solutions, suited for edge and embedded environments
- Proven commercial viability through licensing to a strategic partner for ultra‑high‑performance processor implementation
- Patent‑backed innovations covering time counters, vector data buffers, and extended register sets to protect the technology stack