Silicon Creations provides silicon‑proven analog mixed‑signal IP blocks—including PLLs, oscillators, SerDes PMAs, and LVDS interfaces—qualified for mass production across process nodes from 2 nm to 180 nm. The portfolio offers low‑power, low‑jitter clocking and high‑speed I/O solutions with detailed models, RTL‑based calibration functions, and optional customization, helping ASIC/SoC designers reduce integration risk and accelerate time‑to‑market for smartphones, wearables, networking, automotive, IoT, and medical devices.
Funding
Funding not disclosed
Founders
Product
Problem
Chip designers face high risk and long development cycles when integrating timing, clocking, and high-speed I/O functions into SoCs, especially across advanced process nodes from 2 nm to 180 nm. Limited access to proven, low‑power, low‑jitter PLLs, SerDes, and LVDS IP can cause performance shortfalls, increased silicon cost, and delayed time‑to‑market.
Solution
Silicon Creations supplies a portfolio of silicon‑proven analog mixed‑signal IP blocks—including versatile ring and LC PLLs, free‑running and crystal oscillators, multi‑protocol SerDes PMAs, and bi‑directional LVDS interfaces—qualified for mass production in leading foundries from 2 nm to 180 nm. The IP is delivered with detailed silicon‑calibrated models, RTL‑based auxiliary functions (spread‑spectrum, jitter cleaning, monitoring), and optional semi‑customization to meet specific performance or area targets. Comprehensive design‑verification flows and a global network of qualified partners provide low‑risk integration, rapid qualification, and support for automotive functional‑safety standards (ISO 26262, ISO 9001). This enables customers to reduce development risk, achieve low power and low jitter requirements, and accelerate product launch across smartphones, wearables, networking, automotive, and IoT markets.
Target Audience
Primary customers are semiconductor companies and ASIC/SoC design teams developing high‑performance, low‑power products for smartphones, wearables, networking, automotive, IoT, and medical devices.
Features
- General‑purpose and optimized ring PLLs (fractional‑N, low‑area, low‑bandwidth, low‑jitter, deskew, multi‑phase) covering 32 kHz‑several GHz with sub‑ps jitter performance
- Fully integrated LC PLLs delivering ultra‑low jitter comparable to discrete solutions
- RTL‑based spread‑spectrum modulators, jitter cleaners, jitter monitors, and digital phase aligners for enhanced clock management
- High‑speed SerDes PMAs supporting >30 protocols (PCIe 1‑5, Ethernet, CPRI, JESD204, V‑by‑One, etc.) with programmable serialization widths, low‑latency (<13 UI), burst‑mode CDR, adaptive equalization, and on‑die Xtal reference generation
- Bi‑directional LVDS I/Os operating up to 3 Gb/s, with on‑die termination, dynamic phase alignment, and compatibility with LVPECL and various video standards (FPD‑Link, Camera‑Link, OpenLDI)
- Free‑running and crystal oscillators offering low power, precise PVT‑stable reference clocks for SoC timing and ADC/AFE synchronization
- Analog glue functions (differential buffers, multiplexers, power‑on‑reset, bandgap circuits) for robust clock distribution and system initialization
- Automotive‑qualified IP with documentation and safety compliance (ISO 26262) for functional‑safety critical designs