Signature IP licenses network-on-chip (NoC) intellectual property (IP) solutions optimized for performance, power, and area. Their coherent and non-coherent NoCs enable efficient on-chip communication for complex system-on-chip (SoC) designs.
Funding
Funding not disclosed
Founders
Product
Problem
Modern System-on-Chips (SoCs) face increasing complexity and size, making traditional on-chip bus architectures inadequate for efficient data routing. This complexity leads to bottlenecks, increased power consumption, and limitations in scalability. Exploring the design space for optimal architecture is difficult and time-consuming.
Solution
Signature IP provides Network-on-Chip (NoC) intellectual property (IP) solutions and a comprehensive platform for SoC design, enabling fast, flexible, and configurable interconnects. Their offerings include the iNoCulator TM, a cloud-based EDA tool for defining NoC topology, configuring parameters, and simulating performance metrics like throughput, latency, power, and area. The NoC solutions employ packet switching and layered communication protocols, supporting more concurrent communication channels than traditional bus architectures. Signature IP's NoCs are designed to be easily configurable, allowing customers to experiment with different topologies and settings, and generate top-level RTL code for integration with EDA and FPGA environments.
Target Audience
The primary target audience includes SoC designers and architects in need of efficient and scalable on-chip communication solutions, as well as companies developing complex SoCs for various applications.
Features
- iNoCulator TM: Cloud-based EDA tool for NoC topology definition, configuration, and simulation.
- Supports non-coherent (NC-NoC) and coherent (C-NoC) network architectures.
- Configurable NoC topologies: ring, mesh, concentrated mesh, and torus.
- Supports interface protocols: CHI, ACE, AXI, AHB, APB.
- Scalable, physically-aware network with automatic physical partitioning and auto-pipelining.
- Multiple clocking schemes, including GALS (Globally Asynchronous Locally Synchronous).
- Power control with power island generation and UPF (Unified Power Format) output.
- NC-NoC: Layered, scalable, physically aware configurable NoC supporting multiple clocking schemes and protocols such as AXI4/3, AHB, APB, AXI-lite with bus widths from 32 to 2048 bits.
- C-NoC: Coherent NoC technology supporting mesh, grid and torus topologies with on-chip L3 cache support and protocols including CHI, AXI4/3, AXI-lite, ACE and ACE-lite with bus widths from 32 to 2048 bits.