SEMIQA provides an analog in‑memory accelerator that performs matrix‑vector operations directly within configurable synapse crossbars, reducing data movement and energy consumption. The platform delivers sub‑nanosecond latency with >10× lower energy per operation than digital ASICs, supports on‑chip learning, and includes a software stack that maps TensorFlow/PyTorch models to analog kernels for edge and data‑center deployments.
Funding
Funding not disclosed
Founders
Product
Problem
Conventional digital processors incur substantial energy and latency penalties because data must be shuttled repeatedly between separate memory and compute units. This data‑movement bottleneck limits the scalability of high‑performance AI workloads, especially in power‑constrained edge and data‑center environments. As AI models grow larger, the inefficiency of binary‑only architectures becomes a critical cost driver.
Solution
SEMIQA delivers a neuromorphic analog accelerator that embeds computation directly within the memory substrate, eliminating most data transfers. By leveraging continuous‑valued analog signal processing, the platform executes matrix‑vector operations with sub‑nanosecond latency while consuming a fraction of the power of comparable digital ASICs. The hardware implements configurable synapse arrays that emulate key brain principles such as sparsity and event‑driven activation, enabling both inference and on‑chip learning. An open‑source software stack translates standard AI frameworks (e.g., TensorFlow, PyTorch) into analog-friendly kernels, allowing developers to deploy models without extensive hardware redesign. The solution scales from edge modules to rack‑mount systems, providing a unified path for energy‑efficient AI across diverse form factors.
Target Audience
Primary customers are AI hardware OEMs, edge device manufacturers, and data‑center accelerator integrators seeking ultra‑low‑power, high‑throughput compute for neural network workloads. Research institutions developing neuromorphic algorithms also benefit from the platform’s on‑chip learning capabilities.
Features
- In‑memory analog compute fabric with configurable crossbar synapse arrays for high‑density matrix operations
- Continuous‑time signal processing that supports sub‑threshold operation, achieving >10× lower energy per operation versus digital counterparts
- On‑chip learning primitives (e.g., spike‑timing dependent plasticity, gradient‑based updates) for adaptive inference at the edge
- 16‑bit effective analog precision with built‑in calibration and drift compensation to maintain model accuracy over temperature variations
- Modular tile architecture that can be stacked to scale from single‑chip prototypes to multi‑kilowatt data‑center accelerators
- Compatibility layer (C++/Python API) that maps TensorFlow/PyTorch graphs to analog kernels, reducing integration effort
- Secure data path with hardware‑level encryption for in‑flight analog signal transmission between tiles
- Real‑time monitoring dashboard exposing power, utilization, and analog health metrics via standard REST endpoints