Seminovaa is a deep-tech semiconductor design services company that provides end-to-end ASIC/SoC design, verification, physical implementation, DFT, and post-silicon validation. The company integrates Gen-AI and Agentic-AI models into design workflows to accelerate iterations and improve first-pass silicon success. Its services span RTL design, UVM-based verification, RTL-to-GDSII physical design, and custom analog/mixed-signal layout.
Funding
Funding not disclosed
Founders
Product
Problem
Semiconductor companies face increasing design complexity and time-to-market pressure, with traditional verification and physical implementation workflows often requiring multiple costly silicon iterations. First-pass silicon success remains challenging due to timing closure issues, verification gaps, and the difficulty of validating designs across PVT corners and high-speed interfaces.
Solution
Seminovaa provides comprehensive semiconductor design services covering the full chip development lifecycle, from SoC/ASIC design and verification through RTL-to-GDSII physical implementation, DFT insertion, and post-silicon validation. The company employs industry-standard methodologies like UVM for functional verification and integrates Gen-AI/Agentic-AI models into implementation stages to accelerate iterations and improve design quality. Their physical design expertise includes synthesis, floorplanning, clock tree synthesis, and sign-off closure, while post-silicon services cover silicon bring-up, ATE program development, and yield analysis. The company also offers custom analog/mixed-signal layout design with precision techniques for device matching, symmetry, and shielding to ensure manufacturability and first-pass silicon success.
Target Audience
Primary customers are global semiconductor companies, including startups, mid-size product companies, and large enterprises, that need ASIC/SoC design, verification, physical implementation, or post-silicon validation expertise.
Features
- SoC/ASIC design covering RTL design, IP integration, low-power architecture, and multi-voltage design
- Verification services using SystemVerilog, UVM, and protocol verification for PCIe, DDR, Ethernet, and AMBA interfaces
- AI-enhanced verification workflows integrating Gen-AI/Agentic-AI models to reduce debug cycles and improve coverage
- RTL-to-GDSII physical design including synthesis, floorplanning, placement, routing, CTS, and power planning
- DFT insertion, scan chain stitching, ATPG generation, and STA validation across multiple corners and modes
- Post-silicon validation covering silicon bring-up, ATE program development, high-speed interface validation (PCIe, DDR, Ethernet), and yield analysis
- Custom analog/mixed-signal layout design for amplifiers, PLLs, ADC/DACs, SERDES, and PHYs with device matching and shielding techniques