Samurai provides an AI-native platform for analog integrated circuit design, allowing engineers to describe a block in natural language and receive a schematic that is sized, simulated, and verified in SPICE. The platform captures tacit design knowledge to accelerate workflows, claiming 7x faster schematic generation and 80% lower engineering overhead. It targets the analog bottleneck in ASIC development, where 10% of chip area consumes 90% of design time.
Funding
Funding not disclosed
Founders
Product
Problem
Analog circuit design remains a manual, time-intensive bottleneck in ASIC development, with 10% of chip area consuming 90% of design time. Unlike digital design, which was transformed by synthesis in the 1980s, analog has never been meaningfully automated due to its perceived incomputability, and experienced specialists are retiring faster than they can be replaced.
Solution
Samurai offers an AI-native platform that converts natural-language design specifications into complete analog schematics that are sized, simulated, and verified in SPICE. The system uses a domain-aware foundation pre-contextualized with analog knowledge, enabling engineers to explore and evaluate design concepts through AI-assisted iteration. Each session produces a complete design package with full deliberation histories and documentation, ready for bug-fixing or future alterations. The platform preserves decades of analog design intuition and puts it to work, delivering 7x faster schematic generation, 80% lower engineering overhead, and 20% cost savings compared to legacy workflows.
Target Audience
Primary customers are analog and mixed-signal IC design teams at semiconductor companies and electronics manufacturers who need to accelerate design cycles and reduce reliance on scarce senior analog expertise.
Features
- Natural-language design input that generates sized, simulated, and SPICE-verified schematics
- Domain-aware foundation engine pre-contextualized with analog design knowledge
- AI-assisted iteration for rapid exploration and evaluation of design concepts
- Complete design bundles including deliberation histories and design documentation
- Live schematic rendering with net-level inspection and downloadable design bundles
- Demonstrated capability on real designs such as an LDO regulator on 180 nm CMOS