Rise Design Automation provides a multi-language, high-level synthesis and verification suite that integrates SystemVerilog, C++, and SystemC, along with a generative AI Advisor to enhance hardware design productivity. The platform addresses the stagnation in semiconductor design methodologies by enabling faster implementation and improved verification confidence, crucial for meeting the growing demand in the semiconductor market.
Funding
Funding not disclosed
Founders
Product
Problem
The semiconductor industry faces increasing demand driven by AI, 5G, and smart devices, but hardware design methodologies have stagnated, and a shortage of hardware engineers is projected. Existing hardware design abstractions have not been widely adopted, hindering productivity improvements needed to meet market demands.
Solution
Rise Design Automation offers a multi-language, high-level synthesis, verification, debug, and analysis suite to overcome the limitations of traditional RTL design. The platform supports SystemVerilog, C++, and SystemC, enabling designers to work at higher levels of abstraction. Rise leverages generative AI and other technologies to deliver predictable and superior Quality of Results (QoR) without requiring specialized expertise. By improving simulation speed and verification productivity, Rise enhances verification confidence through seamless integration with various design languages and abstraction levels.
Target Audience
The primary target audience includes semiconductor companies and hardware design teams seeking to improve productivity, reduce design cycles, and meet the growing demand for complex semiconductor devices.
Features
- Multi-language support for SystemVerilog, C++, and SystemC
- High-Level Synthesis (HLS) with Generative AI Advisor for automated code generation
- Predictable Quality of Results (QoR) without requiring high-level design expertise
- SystemVerilog-based verification methodologies
- Seamless integration with existing design environments
- Comprehensive debug and analysis tools
- Leverages Clang, Verific, Microsoft Visual Studio, Google XLS, and Cody