RED Semiconductor builds VISC™, a purpose‑built compute architecture that embeds a high‑performance matrix‑multiply engine directly into a RISC‑V core. The design delivers up to 100× acceleration for AI and signal‑processing workloads while keeping power consumption ultra‑low and providing built‑in security, enabling edge devices to run real‑time inference and cryptography locally. It targets SoC designers and system builders developing edge AI for automotive, smart energy, telecom, and healthcare applications.
Funding
Funding not disclosed
Founders
Product
Problem
Edge devices such as sensors, automotive systems, and IoT appliances require real-time AI and signal processing but are constrained by limited power, latency, and security requirements. Traditional processors rely on separate accelerators or cloud inference, leading to higher energy consumption, increased data transfer, and delayed responses.
Solution
RED Semiconductor offers VISC™, a purpose‑built compute architecture that integrates a high‑performance matrix‑multiply engine directly into a RISC‑V core. By providing inline flow‑control acceleration, VISC reduces clock cycles and memory accesses, delivering up to 100× speedup for core AI and signal‑processing kernels while keeping power usage ultra‑low. The architecture is ISA‑flexible, security‑ready, and designed for continuous, real‑time data streams, enabling edge devices to perform inference and cryptographic tasks locally without relying on external accelerators or cloud services.
Target Audience
Primary customers are semiconductor SoC designers, IP integrators, and system builders developing edge AI, secure automotive, smart energy, telecommunications, and healthcare devices that require high‑performance, low‑power processing.
Features
- Inline acceleration engine that embeds matrix‑multiply and other math kernels directly into the execution path, eliminating separate accelerator blocks
- Up to 100× acceleration on foundational matrix‑multiply operations, a key workload for AI and signal processing
- RISC‑V based design with ISA extensibility, allowing seamless integration into existing RISC‑V ecosystems
- Reduced code size through abstracted instructions that compress complex algorithmic work
- Built‑in security features for trusted, real‑time processing of sensitive data
- Ultra‑low power consumption optimized for constrained edge devices