Qolumbus builds hybrid quantum chips that combine superconducting transmon qubits with semiconductor spin qubits on a CMOS‑compatible substrate, delivering gate fidelities above 99.9 % and modular scalability. The integrated architecture provides fast gate operations, long‑coherence memory, and built‑in error‑correction primitives, supported by a cloud‑based calibration suite and cryogenic control interface for quantum hardware OEMs and cloud providers.
Funding
Funding not disclosed
Founders
Product
Problem
Current quantum computing hardware faces a fundamental trade‑off: superconducting qubit platforms achieve high gate speeds but suffer from limited coherence and scaling challenges, while semiconductor spin qubits offer long coherence but lack mature control infrastructure. This results in processors that are neither reliably high‑fidelity nor scalable to the thousands of qubits needed for practical algorithms. Consequently, error‑correction overheads remain prohibitive for near‑term applications.
Solution
Qolumbus addresses this gap by engineering a hybrid quantum chip that integrates superconducting transmon qubits with semiconductor spin qubits on a single substrate. The architecture leverages the fast gate operations of superconducting circuits together with the long coherence times of spin qubits, enabling a unified platform that balances speed and stability. By co‑designing the control stack and the physical layout, the company delivers gate fidelities exceeding 99.9 % while supporting modular scaling to larger qubit arrays. The hybrid approach also simplifies quantum error correction, as spin qubits can serve as low‑error memory nodes within a superconducting processor. Qolumbus fabricates these chips using CMOS‑compatible processes, allowing volume production and integration with existing cryogenic control hardware. A cloud‑based calibration and diagnostics suite automates performance tuning, reducing the expertise required to operate the system. Together, these elements provide a pathway toward reliable, large‑scale quantum processors for both research and commercial workloads.
Target Audience
Primary customers are quantum hardware OEMs, national labs, and cloud‑based quantum service providers seeking high‑fidelity, scalable processors for algorithm development and error‑corrected computation. The solution also serves advanced research institutions that require integrated, low‑error qubit platforms for experimental protocols.
Features
- Integrated hybrid architecture combining superconducting transmons and semiconductor spin qubits on a monolithic die
- Gate fidelity > 99.9 % achieved through cross‑platform pulse shaping and synchronized control electronics
- Scalable modular layout supporting incremental addition of qubit tiles without redesigning the full chip
- Built‑in quantum error‑correction primitives that exploit spin qubits as long‑lived memory registers
- CMOS‑compatible fabrication flow enabling high‑volume manufacturing and cost‑effective scaling
- Cryogenic control interface compatible with Quantum Machines’ IQCC system for low‑latency pulse delivery
- Cloud‑hosted calibration platform that performs automated benchmarking, drift compensation, and performance analytics
- Secure, end‑to‑end encrypted data pipeline for result export to quantum cloud services via standard QIR/QASM APIs