PowerLattice
PowerLattice delivers a monolithic power-delivery chiplet that embeds voltage regulation directly inside the processor package, just micrometers from the compute die. Its Rainier micro-IVR architecture combines on-die magnetic inductors, advanced control circuits, and a programmable software layer to cut conduction losses by over 50% and reduce power noise by an order of magnitude, enabling up to 2× performance uplift under fixed data-center power budgets.
- Semiconductor
- Hardware
Funding
Raised to date
$111MRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
across 2 rounds
PG$86M · Undisclosed
Announced Oct 2026 · from article date
Disclosed cumulative: $111M
Founders
Founder details are not available yet.
Product
Problem
AI accelerators and high-performance GPUs are approaching multi-kilowatt power levels, but conventional power-delivery architectures route large currents over long PCB and substrate traces. The resulting conduction losses, excess heat, and voltage noise create a "power wall" that limits compute density and raises cooling costs in data-center deployments.
Solution
PowerLattice delivers a monolithic power-delivery chiplet that embeds voltage regulation directly inside the processor package, only a few hundred micrometers from the compute die. The chiplet combines proprietary on-die magnetic inductors (PowerMagix™), advanced analog control circuits with Programmable Power Array (P²A™) synchronization, and a programmable software layer on a single silicon die, shortening the power path to near-zero length. This tight coupling cuts conduction loss by more than 50% and reduces power noise by an order of magnitude compared to conventional motherboard power delivery, enabling higher power ceilings and 2-3× better performance-per-watt for AI workloads. The architecture is vertically stacked and fully configurable, allowing multiple chiplets to be tiled in parallel to match any SoC power topology. Fabrication tolerances control the chiplet's z-height in the low-hundreds-of-micrometers range, supporting land-side, substrate-side, or interposer-embedded integration schemes. The result is a scalable, low-impedance power solution that improves efficiency, reliability, and thermal headroom for next-generation compute platforms.
Target Audience
Primary customers are AI accelerator designers, GPU and high-performance compute ASIC vendors, and data-center SoC architects seeking to overcome power-budget constraints and improve thermal efficiency.
Features
- On-die planar magnetic inductors (miniaturized "Rainier" micro-IVR) delivering up to 5 A/mm² current density
- Integrated analog voltage-control loop with fast transient response for dynamic AI workloads
- Programmable software layer for per-chiplet voltage regulation, power-noise filtering, and telemetry
- Vertical monolithic chiplet form factor with configurable z-height (hundreds of micrometers) for flexible package integration (land-side, substrate, or interposer)
- Parallel-scalable architecture: multiple chiplets can be tiled to cover any power domain size or shape
- High-efficiency power conversion achieving >50% reduction in effective compute power consumption
- Built-in diagnostics and real-time monitoring exported via standard I²C/SMBus interfaces for data-center management systems