PowerLattice provides a monolithic power‑delivery chiplet that integrates voltage regulation, on‑die magnetic inductors, and analog control directly within the processor package. By shortening the power path to a few hundred micrometers, it cuts conduction loss by over 50 % and improves performance‑per‑watt for AI accelerators, with a programmable software layer and scalable tiling for any SoC power topology.
Funding
Funding not disclosed
Founders
Product
Problem
AI accelerators and high‑performance GPUs are approaching multi‑kilowatt power levels, but conventional power‑delivery architectures route large currents over long PCB and substrate traces. The resulting conduction losses, excess heat, and voltage noise create a “power wall” that limits compute density and raises cooling costs in data‑center deployments.
Solution
PowerLattice delivers a monolithic power‑delivery chiplet that embeds voltage regulation directly inside the processor package, only a few hundred micrometers from the compute die. The chiplet combines proprietary on‑die magnetic inductors, advanced analog control circuits, and a programmable software layer on a single silicon die, shortening the power path to near‑zero length. This tight coupling cuts conduction loss by more than 50 % and reduces power‑noise, enabling higher power ceilings and 2‑3× better performance‑per‑watt for AI workloads. The architecture is vertically stacked and fully configurable, allowing multiple chiplets to be tiled in parallel to match any SoC power topology. Fabrication tolerances control the chiplet’s z‑height in the low‑hundreds‑of‑micrometers range, supporting land‑side, substrate‑side, or interposer‑embedded integration schemes. The result is a scalable, low‑impedance power solution that improves efficiency, reliability, and thermal headroom for next‑generation compute platforms.
Target Audience
Primary customers are AI accelerator designers, GPU and high‑performance compute ASIC vendors, and data‑center SoC architects seeking to overcome power‑budget constraints and improve thermal efficiency.
Features
- On‑die planar magnetic inductors (miniaturized “Rainier” micro‑IVR) delivering up to 5 A/mm² current density
- Integrated analog voltage‑control loop with fast transient response for dynamic AI workloads
- Programmable software layer for per‑chiplet voltage regulation, power‑noise filtering, and telemetry
- Vertical monolithic chiplet form factor with configurable z‑height (hundreds of micrometers) for flexible package integration (land‑side, substrate, or interposer)
- Parallel‑scalable architecture: multiple chiplets can be tiled to cover any power domain size or shape
- High‑efficiency power conversion achieving >50 % reduction in effective compute power consumption
- Built‑in diagnostics and real‑time monitoring exported via standard I²C/SMBus interfaces for data‑center management systems