Ponos Technology provides hardware‑software co‑designed solutions that accelerate post‑quantum cryptographic primitives and zero‑knowledge proof (ZKP) workloads. Its RISC‑V CryptoCPU and a library of IP cores deliver vectorized, low‑power processing for FPGA and ASIC integration, while its proving infrastructure services enable high‑throughput, low‑latency verifiable computation for security‑critical systems.
Funding
Funding not disclosed
Founders
Product
Problem
Current cryptographic hardware struggles to provide the performance, energy efficiency, and scalability required for post-quantum zero‑knowledge proof (ZKP) workloads, leading to high costs and limited deployment in security‑critical systems.
Solution
Ponos Technology delivers hardware‑software co‑designed solutions that accelerate post‑quantum cryptographic primitives and ZKP computations. Their RISC‑V CryptoCPU integrates vectorized post‑quantum processing to execute fast, cost‑effective zero‑knowledge proofs without needing system migration. Complementary IP blocks—such as hash functions, NTT‑based lattice arithmetic, and MSM modules—offer best‑in‑class performance and low power for integration into FPGAs and ASICs. Ponos also provides end‑to‑end proving infrastructure services, designing and deploying high‑throughput, low‑latency verification platforms on programmable hardware. Through ongoing research, they create hardware‑friendly, sustainable hash functions and optimized arithmetic cores to further improve the efficiency of zkSTARK and zkSNARK implementations.
Target Audience
Primary customers are semiconductor designers, FPGA/ASIC vendors, and security‑focused enterprises that require efficient, post‑quantum‑resistant cryptographic acceleration for zero‑knowledge proof workloads.
Features
- RISC‑V CryptoCPU with vectorized post‑quantum instruction set for accelerated ZKP generation
- Library of post‑quantum cryptographic IP cores (hashes, NTT/iNTT, lattice arithmetic, MSM) optimized for area and energy efficiency
- FPGA‑based proving infrastructure delivering high‑throughput, low‑latency verifiable computation
- Hardware‑software co‑design methodology that minimizes migration overhead and maximizes performance on custom SoCs
- Research‑driven development of hardware‑friendly, sustainable hash functions for zkSTARK/SNARK applications