PIMIC provides a processing‑in‑memory silicon platform that embeds multiply‑accumulate operations in SRAM/DRAM cells, enabling continuous speech‑recognition inference on edge devices with sub‑50 µA power consumption and deterministic sub‑millisecond latency. The architecture delivers up to 20 TOPS · mm⁻² (≈50× higher throughput than conventional CPUs) while maintaining <2 % false‑accept/reject rates, and integrates with TinyML toolchains for easy OEM integration.
Funding
Funding not disclosed
Founders
Product
Problem
Edge AI inference, particularly continuous speech recognition, is constrained by the high power draw and limited compute density of conventional semiconductor architectures, making it difficult to deploy always‑on voice interfaces in battery‑powered or ultra‑low‑power devices.
Solution
PIMIC delivers a processing‑in‑memory (PIM) silicon platform that relocates compute primitives into the memory array, eliminating the costly data movement between separate CPU and DRAM blocks. This architecture achieves up to 50× higher compute throughput while cutting power consumption by a factor of 20, enabling speech‑recognition inference at less than 50 µA—approximately one‑twentieth the energy of current state‑of‑the‑art solutions. The on‑chip pipeline processes audio signals to inference results securely within the same die, providing deterministic latency and high accuracy (<2 % false accept and reject rates). The design is fabricated in a 22 nm CMOS process, delivering 20 TOPS per mm², and is engineered for seamless scaling to more advanced process nodes. By integrating directly into edge devices, PIMIC’s solution supports real‑time, privacy‑preserving voice interfaces without compromising battery life.
Target Audience
Primary customers are OEMs and system integrators developing battery‑operated voice‑enabled IoT devices, wearables, and other edge AI products that require ultra‑low‑power, on‑device inference.
Features
- Processing‑in‑memory compute fabric that embeds multiply‑accumulate operations within SRAM/DRAM cells, removing external memory bandwidth bottlenecks.
- Power envelope under 50 µA for continuous speech‑recognition workloads, achieved through in‑memory data reuse and voltage‑scaled operation.
- Compute density of 20 TOPS · mm⁻² at 22 nm node, providing up to 50× performance uplift versus traditional micro‑architectures.
- On‑chip audio front‑end and inference pipeline delivering end‑to‑end latency in the sub‑millisecond range with deterministic timing.
- Accuracy guarantees with false‑accept and false‑reject rates below 2 % per hour for voice command detection.
- Secure, isolated processing path from microphone input to model output, eliminating external data exposure.
- Scalable design methodology that can be ported to finer‑node CMOS processes, preserving the PIM advantage across technology generations.
- Compatibility with TinyML toolchains and standard AI model formats for rapid integration into existing edge software stacks.