Panmnesia provides a full‑stack link solution for AI data centers, combining CXL 3.2‑compliant switch silicon, silicon IP, hardware switches, and orchestration software to create a low‑latency, high‑throughput interconnect fabric. The platform supports dynamic pooling and sharing of compute and memory resources across disaggregated systems, with additional connectivity options such as UALink and Ethernet, enabling scalable AI workloads while reducing power consumption and operational costs.
Funding
$57M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
1OICFounders
Product
Problem
Modern AI workloads require multiple accelerators and heterogeneous resources, leading to significant communication overhead and inflexible system architectures that hinder scalability and cost efficiency in data centers and HPC environments.
Solution
Panmnesia delivers a full‑stack link solution that spans silicon IP, hardware switches, system integration, and software orchestration to create a low‑latency, high‑throughput fabric for AI infrastructure. By implementing the CXL 3.2 standard with port‑based routing and supporting additional interconnects such as UALink and Ethernet, the solution enables dynamic pooling, expansion, and sharing of compute and memory resources across disaggregated systems. Advanced architectural optimizations reduce power consumption and latency, while a robust software layer automates resource allocation and management, allowing workloads to scale seamlessly without manual intervention. This approach provides true composability, minimizing both capital and operational expenditures for large‑scale AI deployments.
Target Audience
Primary customers are AI hardware manufacturers, data‑center operators, and HPC system integrators seeking a scalable, low‑latency interconnect fabric for multi‑accelerator workloads.
Features
- Industry‑first switch silicon fully compliant with CXL 3.2, featuring port‑based routing for deterministic data paths
- Integrated silicon IP library optimized for minimal latency and power across the AI link fabric
- High‑fanout switch topology supporting massive scale‑out of accelerators and memory modules
- Interoperable connectivity options including CXL, UALink, and Ethernet to accommodate diverse system requirements
- End‑to‑end software stack that automates resource discovery, allocation, and dynamic reconfiguration of compute and memory pools
- Comprehensive monitoring and management APIs for reliable operation in data‑center and HPC settings