OptoSwift builds chip‑scale photonic neural network accelerators that perform AI inference directly in optical hardware rather than adding intelligence in software. Their foundry‑compatible photonic chips combine in‑memory computing with one‑shot inference, delivering around 400 million parameters per mm², ultra‑low latency and energy use, by breaking the memory wall they achieve orders‑of‑magnitude lower energy per operation, and a scalable architecture for edge and data‑center workloads.
Funding
Funding not disclosed
Founders
Product
Problem
AI inference systems are constrained by the separation of memory and compute, which creates bandwidth bottlenecks, high latency, and elevated energy consumption, limiting scalability for both edge devices and data‑center accelerators.
Solution
OptoSwift delivers chip‑scale photonic neural networks that perform inference directly in optical hardware, merging memory and compute into a single substrate. The optical architecture enables one‑shot inference, removing the need for data shuttling between separate memory and processor units and thereby reducing latency and power per operation. With an estimated density of about 400 million parameters per square millimeter, the chips provide high computational throughput in a compact form factor. The technology is designed for foundry‑compatible manufacturing, allowing integration into existing semiconductor supply chains for edge AI modules and data‑center accelerator cards. By using passive photonic components, the platform scales performance without the thermal limits typical of electronic ASICs, supporting workloads such as computer vision, speech processing, and sensor analytics.
Target Audience
Primary customers are semiconductor manufacturers, AI accelerator vendors, and system integrators developing edge AI hardware or data‑center inference platforms that require high‑density, low‑latency, and energy‑efficient compute.
Features
- Photonic neural‑network chips that combine storage and compute in an optical medium
- One‑shot inference eliminating intermediate data movement between memory and processor
- Parameter density of ~400 M parameters per mm² for high throughput in a small footprint
- Low latency and low energy consumption compared with conventional electronic accelerators
- Scalable architecture suitable for both edge devices and data‑center accelerator deployments
- Foundry‑compatible manufacturing process enabling integration with standard semiconductor fabs