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OPENEDGES Technology

OPENEDGES Technology offers integrated memory subsystem IP solutions for ASIC and ASSP development. Their IP suite, including DDR PHY, memory controllers, and interconnects, optimizes power, silicon area, and DRAM performance for advanced computing applications.

Seoul, South KoreaFounded 20151143K+ followers
Updated 4 months ago

Funding

$90.9M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.

Funding rounds are not available yet.

Founders

Product

Problem

Developing System-on-Chips (SoCs) for advanced computing applications requires efficient memory subsystems that optimize power consumption, silicon area, and DRAM performance. Integrating these complex memory interfaces and controllers into ASIC and ASSP designs presents significant engineering challenges, impacting overall system efficiency and time-to-market.

Solution

OPENEDGES Technology provides a comprehensive suite of integrated memory subsystem Intellectual Property (IP) solutions designed to address these challenges. Their IP offerings are engineered for seamless integration into ASIC and ASSP development flows, enabling designers to achieve enhanced power efficiency, reduced silicon footprint, and optimized DRAM performance. By leveraging OPENEDGES' IP, clients can accelerate their SoC development cycles and improve overall system resource utilization. The company's focus on practical, scalable, and maintainable IP ensures long-term growth and alignment with OEM requirements.

Target Audience

The primary target audience includes semiconductor companies and system integrators developing ASICs and ASSPs for smart computing, AI edge computing, and other high-performance applications.

Features

  • Integrated Memory Subsystem IP Platform, including interconnect, memory controller, and PHY components.
  • DDR PHY IP for high-speed memory interface connectivity.
  • DDR Memory Controller IP for managing DRAM operations.
  • NoC (Network-on-Chip) Bus Interconnect IP for efficient on-chip data transfer.
  • NPU (Neural Processing Unit) IP for accelerating AI inference computations.
  • IP solutions designed for synergy, enhancing overall system resource efficiency.
  • Focus on simplicity, scalability, and maintainability in IP design.
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