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Oboe

Oboe offers an FPGA‑based prototyping platform that integrates with existing CI/CD pipelines via a single file addition, enabling silicon design teams to run hardware‑accurate verification, detect hard‑to‑simulate bugs, and benchmark real software workloads. It supports SystemVerilog, C/C++, and Python testbenches, provides secure encryption and access controls, and includes modern collaborative interfaces for architects, RTL, and verification engineers.

Updated 2 months ago

Funding

Funding not disclosed

Funding rounds are not available yet.

Founders

Founder details are not available yet.

Product

Problem

Silicon design teams often rely on slow, simulation‑only verification flows that cannot expose complex bugs, accurately measure real‑software performance, or evaluate multiple architectural alternatives quickly. This limits iteration speed and hampers collaboration between architects, RTL engineers, and verification teams.

Solution

Oboe provides an FPGA‑based prototyping platform that integrates with existing CI/CD pipelines through a single file addition to a design. By running designs on actual hardware, engineers can detect hard‑to‑simulate bugs, benchmark real software workloads, and explore candidate architectures in parallel. The platform supports SystemVerilog, C/C++, and Python, allowing cocotb testbenches to run unchanged. Secure encryption and access controls protect IP while modern, collaborative interfaces enable commenting and third‑party tool integration, delivering faster, more reliable verification without disrupting established workflows.

Target Audience

Primary users are silicon design teams, including architects, RTL engineers, and verification engineers, at semiconductor companies and hardware startups that need rapid, hardware‑accurate verification.

Features

  • One‑file integration that adds FPGA prototyping to any CI/CD flow
  • Full language support for SystemVerilog, C/C++, and Python (cocotb) testbenches
  • Real‑hardware execution for accurate performance measurement of software workloads
  • Parallel architecture evaluation to accelerate design space exploration
  • Secure encryption and granular access controls to safeguard IP during collaboration
  • Modern, intuitive UI with commenting and integration hooks for software‑engineer‑style collaboration
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