Novomorphic provides end‑to‑end engineering of custom ASIC/SoC and mixed‑signal subsystems for edge devices that require deterministic AI inference, real‑time control, and functional safety. By co‑designing silicon, analog front‑ends, and firmware from system constraints, it delivers power‑efficient, safety‑certified hardware compliant with standards such as ISO 26262 and ITAR‑free requirements for defence, automotive, telecom, energy and industrial automation OEMs.
Funding
Funding not disclosed
Founders
Product
Problem
Edge devices that must acquire sensor data, perform AI inference, and execute real‑time control often rely on separately sourced components and ad‑hoc integration. This fragmented approach makes it difficult to meet strict power budgets, latency targets, functional‑safety standards, and security requirements, especially in regulated sectors such as defence, automotive, telecoms, energy and industrial automation.
Solution
Novomorphic delivers a system‑first engineering methodology that designs custom silicon and electronic subsystems together as a single, deterministic platform. By starting from defined system constraints—latency, power, thermal envelope, safety and lifecycle—its engineers partition functionality between ASIC/SoC blocks and flexible firmware, then co‑design the analog front‑end, compute architecture and real‑time control logic. The resulting integrated solutions provide on‑device AI inference with predictable timing, hardened mixed‑signal data paths, and safety‑aware control loops that comply with standards such as ISO 26262 and ITAR‑free requirements. End‑to‑end services include architecture definition, FPGA prototyping, silicon tape‑out, and post‑silicon validation, enabling customers to deploy edge intelligence in demanding environments without costly redesign cycles.
Target Audience
Primary customers are OEMs and system integrators in defence, aerospace, automotive, telecom, energy and industrial automation that require tightly integrated, safety‑certified edge AI hardware for real‑time sensing, inference and control.
Features
- Custom ASIC/SoC implementation from RTL through verification, FPGA validation and physical realization, optimized for deterministic inference and low‑latency data flow.
- High‑integrity mixed‑signal front‑ends (ADC/DAC, RF front‑ends, sensor interfaces) with analogue‑digital co‑simulation to ensure robust real‑world data acquisition.
- Safety‑aware architectures supporting functional safety (ISO 26262, ASIL) and security toolchains aligned to MoD and allied standards, including ITAR‑free design environments.
- Power‑electronics integration using GaN/SiC compounds and thermal‑aware layouts for high‑efficiency powertrain, battery‑management and grid‑edge applications.
- High‑speed digital interfaces (custom SERDES, PHY) compliant with 3GPP and ORAN specifications for telecom and 5G infrastructure.
- End‑to‑end engineering workflow: system constraint definition, workload analysis, architecture partitioning, prototype validation, and lifecycle support for long‑term deployments.
- UK‑based sovereign design flow with zero offshore access, ensuring secure supply chains for critical national infrastructure.