Neuromorphica provides neuromorphic System‑on‑Chip platforms that combine an event‑driven architecture with an integrated RISC‑V core to deliver sub‑5 ms latency and milli‑watt power consumption for edge AI and software‑defined radio applications. The chips support on‑device learning, secure boot, and flexible sensor and SDR interfaces, enabling OEMs to build autonomous, low‑power devices for robotics, aerospace, and medical wearables.
Funding
Funding not disclosed
Founders
Product
Problem
Edge AI and IoT devices require real-time inference, low latency, and high reliability, yet conventional CPUs and GPUs consume excessive power and generate heat, limiting battery life and form‑factor options for autonomous vehicles, industrial robots, satellite communications, and medical wearables. This energy‑performance mismatch hampers the deployment of intelligent functions at the edge where connectivity is intermittent or security‑critical.
Solution
Neuromorphica delivers European‑designed neuromorphic System‑on‑Chip platforms—NMS731 for general‑purpose edge AI and NMT194 for software‑defined radio (SDR) integration—that combine brain‑inspired event‑driven architectures with a high‑performance RISC‑V core. The chips achieve up to ten‑fold higher compute density while operating at milli‑watt power levels, enabling sub‑5 ms end‑to‑end latency for sensor‑fusion workloads. Built‑in security‑by‑design protects intellectual property and communication channels, and on‑device synaptic plasticity supports continual learning without cloud dependence. Flexible SDR blocks and native sensor interfaces allow rapid reconfiguration for autonomous mobility, industrial automation, aerospace, and medical applications, providing a turnkey SoC that bootstraps next‑generation edge products.
Target Audience
Primary customers are OEMs and system integrators building edge AI/IoT devices, autonomous vehicle platforms, industrial robotics, aerospace/defense communication systems, and next‑generation medical wearables.
Features
- Event‑driven neuromorphic architecture that processes spikes only when data arrives, reducing average power consumption to the milli‑watt range.
- Integrated high‑performance RISC‑V CPU with end‑to‑end latency < 5 ms and reaction speed 10–100× faster than traditional microcontrollers.
- On‑chip synaptic plasticity enabling on‑device learning and adaptation for autonomous operation.
- Security‑by‑design IP protection, secure boot, and encrypted communication pathways for tamper‑resistant deployments.
- Native SDR transceiver (NMT194) with flexible protocol stack for real‑time spectrum agility and low‑latency signal processing.
- Multi‑modal sensor fusion support (vision, lidar, radar, acoustic) through dedicated high‑speed I/O and parallel processing pipelines.
- Scalable SoC footprint and power envelope suitable for ultra‑compact IoT nodes, mobile robots, and satellite payloads.