Memtech provides pre‑validated memory subsystem IP blocks and reference designs for HBM3E, LPDDR5x, GDDR, and MRAM‑DDR, enabling rapid integration into SoCs. Its ecosystem includes automated build tools, verification suites, FPGA bring‑up kits, and virtual prototyping models, with safety‑graded automotive options and QoS features for data‑center and edge AI workloads, reducing engineering effort by up to 50 % and shortening time‑to‑silicon.
Funding
Funding not disclosed
Founders
Product
Problem
SoC designers must navigate lengthy NRE cycles, complex verification flows, and stringent safety or power constraints when integrating high‑performance memory such as HBM, LPDDR, GDDR, or emerging MRAM‑DDR technologies for data‑center, edge AI, automotive, and graphics applications. These challenges often delay product launches and inflate engineering costs.
Solution
Memtech delivers a portfolio of ready‑to‑integrate Memory Subsystems (MSS) that span HBM3E, LPDDR5x, GDDR, and MRAM‑DDR, each packaged as pre‑validated IP blocks and reference designs. Complementary ecosystem enablement platforms—Turnkey‑MemSoC, Memverify, ProtoDRAM‑FPGA, and MemorySim‑V—provide automated build scripts, verification suites, FPGA bring‑up kits, and virtual prototyping models to accelerate integration and reduce verification effort. Safety‑critical automotive offerings are ASIL‑graded and meet ISO 26262 and ISO 21434 standards, while data‑center solutions include built‑in QoS and high‑bandwidth, low‑latency interfaces. An integrated SDK and comprehensive bring‑up services ensure reliable initialization, yield improvement, and seamless software‑hardware co‑development. Collectively, these assets cut engineering resource usage by up to 50 % and shorten time‑to‑silicon by as much as 15 months, allowing customers to focus on application differentiation rather than low‑level memory design.
Target Audience
The primary customers are SoC architects and design teams in data‑center, edge‑AI, automotive, graphics, and aerospace sectors, as well as semiconductor IP integrators and OEMs building AI accelerators, SSDs, or AR/VR devices that require high‑performance, safety‑qualified memory solutions.
Features
- HBM3E controller and PHY IP delivering up to 1.2 TB/s per stack with sub‑nanosecond latency, fully JEDEC‑compliant.
- LPDDR5x/5 controller, PHY, and verification IP optimized for ultra‑low power, high bandwidth, and ASIL‑grade safety certification (ISO 26262, ISO 21434).
- Turnkey‑MemSoC reference platform integrating pre‑validated controller, soft PHY, AXI transaction engine, and automated build/validation scripts for rapid SoC integration.
- Memverify verification suite (UVM‑based VIP, coverage models, error‑injection) supporting major simulators to accelerate functional verification.
- ProtoDRAM‑FPGA bring‑up kit with pre‑built FPGA bitstream, traffic generators, and known‑good timing files for hardware validation before ASIC tape‑out.
- MemorySim‑V virtual prototyping environment with SystemC‑TLM2 models, HAL APIs, and optional Linux driver for early software development.
- Integrated power‑management and QoS blocks (dynamic voltage/frequency scaling, error correction, self‑tuning PHY) to meet stringent energy budgets in edge and data‑center workloads.