MARASA
MARASA is building software-defined hardware—a chip that rearranges its own internal architecture to optimize the programs it runs, continuously improving performance and reliability after deployment. The on-chip compiler never finishes, locking the program's semantic meaning while iterating on hardware arrangements measured under real workloads. It targets extreme environments like Saturn-orbit missions and high-frequency trading floors.
- Semiconductor
- Hardware
Funding
Raised to date
$120KRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Founder details are not available yet.
Product
Problem
Most silicon is fixed at fabrication, leaving performance and reliability static for the life of the hardware. In extreme environments—such as Saturn-orbit missions or high-frequency trading floors—static chips cannot adapt to changing workloads, degrading performance or failing outright without human intervention.
Solution
MARASA develops software-defined hardware: a chip that rearranges its own internal architecture to optimize execution of loaded programs. The chip continuously searches for better hardware arrangements of the same computation, measuring improvements on actual hardware under real workloads. Every rearrangement is verified against a locked semantic meaning of the original code, ensuring the program's behavior never changes—only its speed and reliability improve. The compiler lives on the chip and never finishes, producing a correct mapping first, then iterating indefinitely. When a region of silicon degrades, the layout drifts away from it, extending operational life. The result is a chip that becomes the program it runs and keeps improving for years after deployment.
Target Audience
Primary customers are organizations deploying compute in extreme environments, including space agencies and satellite operators requiring radiation-tolerant, long-life hardware, and financial trading firms needing ultra-low-latency, high-reliability processing.
Features
- Self-rearranging silicon fabric that evolves its internal layout post-deployment without human intervention
- On-chip compiler that continuously searches for better mappings of the same computation, measured on actual hardware under real workload
- Semantic locking mechanism that preserves exact program behavior while allowing hardware arrangement to change
- Degradation-aware layout drift that routes computation away from failing silicon regions
- Built for extreme environments: Saturn-orbit reliability and sub-microsecond trading floor latency