Lamb Labs
Lamb Labs builds Model Processing Units (MPUs) that hardcode entire AI models, including their weights, directly into silicon to eliminate the memory-bandwidth bottleneck faced by GPUs. The company targets 20,000+ tokens per second and 63× higher intelligence per watt through a four-stage roadmap spanning post-trained software models, FPGA accelerators, and custom ASICs. Its current FPGA prototype runs an 8B-parameter model under 10 watts on an off-the-shelf Kria KV260 board.
- Artificial Intelligence
- Hardware
- Semiconductor
Funding
Founders
Product
Problem
General-purpose AI accelerators like GPUs suffer from a memory-bandwidth bottleneck, as every weight must be moved from memory to compute for each inference step. This constant data movement limits token throughput, increases energy consumption, and prevents models from running efficiently at the edge or in power-constrained environments.
Solution
Lamb Labs is building Model Processing Units (MPUs) that hardcode the entire model, including its weights, into silicon, making the model itself the chip. By eliminating weight movement from the inference loop, the company targets 20,000+ tokens per second and 63× higher intelligence per watt than today's best AI accelerators. The company follows a four-stage roadmap: post-trained software models optimized for on-chip fitting, FPGA accelerators that compile models into custom logic, a fully on-chip proof-of-concept called Little Lamb, and ultimately custom ASICs with hard-coded model architectures. Their RL environment searches chip designs to optimize for speed and energy per token.
Target Audience
Primary customers are AI infrastructure providers, edge computing companies, and enterprises deploying large language models that require high-throughput, low-latency inference with minimal power consumption.
Features
- Woolly: a post-trained Qwen model optimized to be smaller and faster so the entire model fits on-chip, with a public demo comparing text, latency, and throughput against the original Qwen3-8B
- Little Lamb: a self-trained tiny language model with weights burned directly into FPGA fabric, generating every token on a $250 Kria KV260 board with no DRAM in the token loop
- FPGA accelerator prototype running an 8B-parameter model under 10 W on an off-the-shelf Kria KV260 board
- Custom ASIC design targeting 20,000+ tokens per second at 63× higher intelligence per watt
- Reinforcement learning environment that searches chip designs for optimal speed and energy per token
- Full-stack approach spanning software optimization, FPGA compilation, and custom silicon design