L3MATRIX provides a silicon‑photonic switching architecture that co‑packages a large 2‑D optical matrix with a CMOS ASIC, creating a high‑radix, single‑stage, non‑blocking network capable of petabit‑per‑second throughput. The integrated photonic‑digital solution uses single‑mode waveguides to deliver 25 Gb/s per channel with 10‑20 ns latency while reducing power consumption by up to tenfold compared to traditional electronic switches. It targets data‑center equipment manufacturers and operators seeking scalable, low‑power optical interconnects for large‑scale networks.
Funding
Funding not disclosed
Founders
Product
Problem
Data center operators face rapidly increasing intra- and inter‑DC traffic that exceeds the capacity of conventional electronic packet switching and copper interconnects, leading to high power consumption, limited reach, and growing latency.
Solution
L3MATRIX delivers a silicon‑photonic switching architecture that co‑packages a large two‑dimensional optical matrix with a CMOS ASIC, creating a high‑radix, single‑stage, non‑blocking network capable of petabit‑per‑second (Pb/s) throughput. The integrated photonic‑digital “co‑package” uses single‑mode waveguides to provide long‑reach, low‑latency (10‑20 ns) connections while reducing the number of switching devices required. This approach cuts power consumption by roughly tenfold compared with traditional electronic switches and enables scalable, cost‑effective data center networks. The technology is made available through the PhoxLab innovation hub for further development and validation in real data‑center environments.
Target Audience
Primary customers are data center equipment manufacturers and operators seeking high‑performance, energy‑efficient optical interconnect solutions for large‑scale, non‑blocking network architectures.
Features
- Large‑scale 2‑D silicon photonics matrix providing high data density and single‑mode optical reach
- Vertical integration of the optical matrix with a CMOS switching ASIC (co‑package) to increase chip radix
- 25 Gb/s per channel bandwidth with low latency (10‑20 ns) due to reduced switching hops
- Non‑blocking, single‑stage network architecture enabling petabit‑per‑second scaling
- Up to 10× lower power consumption by minimizing the number of switching elements
- Available for SME development and testing via the PhoxLab European Photonics Innovation Hub