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ITDA Semiconductor

ITDA Semiconductor provides no-code, generative system IP tools that automate power, clock, and DFT/IO system design for system-on-chip (SoC) development. Its SOC Canvas platform generates essential deliverables like SDF, UPF, and DFT outputs automatically, enabling engineers to achieve tape-out 25% faster while eliminating data mismatches that cause engineering change orders (ECOs).

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Founded 2022131K+ followers
Updated 16 days ago

Funding

Funding not disclosed

Funding rounds are not available yet.

Founders

Founder details are not available yet.

Product

Problem

As SoCs become more complex, the cost and time required for power, clock, and DFT system design increase significantly. This complexity leads to data mismatches between design stages, which are a major cause of engineering change orders (ECOs) that can severely impact project schedules and budgets.

Solution

ITDA Semiconductor provides SOC Canvas, a no-code based generative system IP platform that automates full-custom SoC system design. The platform consists of three specialized tools: Power Canvas for power system design with built-in DFT and leakage power reduction, Clock Canvas for clock system design with dynamic power reduction, and DFT Canvas for DFT/IO system design with flexible IO DFT networks. SOC Canvas automatically generates essential deliverables such as SDF, UPF, and DFT outputs with high speed while guaranteeing data consistency across all design stages. This approach simplifies complex system design, allowing engineers to work without writing a single line of code and achieve tape-out 25% faster.

Target Audience

Primary customers are semiconductor design teams at fabless companies and integrated device manufacturers who need to streamline SoC system design and reduce time-to-tape-out for complex chips.

Features

  • No-code generative system IP platform that eliminates manual coding for SoC power, clock, and DFT system design
  • Power Canvas supports full-custom power systems with built-in DFT and leakage power reduction capabilities
  • Clock Canvas enables full-custom clock system design with dynamic power reduction features
  • DFT Canvas provides flexible IO DFT network design and generation
  • Automatic generation of SDF, UPF, and DFT deliverables with guaranteed data consistency across design stages
  • Integration of architecture, hardware, and software expertise into a unified design automation framework
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