Irreversible builds fully analog inference chips that perform neural network computations directly within non‑volatile memory, eliminating digital data movement and achieving roughly a thousand‑fold reduction in energy use versus conventional digital AI accelerators. The architecture supports scalable neural topologies—from thousands to millions of neurons—and includes hardware‑aware training tools and an integrated microcontroller for calibration and programmability, enabling ultra‑low‑power, always‑on AI in edge devices, drones, and robotics.
Funding
Funding not disclosed
Founders
Product
Problem
Current AI accelerators rely on digital, von Neumann architectures that consume significant power, limiting deployment of intelligent functions to data centers and preventing on‑device inference in low‑power environments such as sensors, drones, and edge robots.
Solution
Irreversible develops fully analog inference chips that perform neural network computations directly within non‑volatile memory cells. By eliminating digital data movement, the architecture achieves roughly a thousand‑fold reduction in energy consumption compared to conventional digital AI processors. The chips support scalable neural topologies—from thousands to millions of neurons—and include hardware‑aware training tools to mitigate process, voltage, and temperature variations. A lightweight digital microcontroller handles calibration, communication, and programmability, enabling seamless integration as IP, modules, or complete solutions for always‑on sensing and autonomous edge applications.
Target Audience
Primary customers are manufacturers of edge devices, autonomous drones, robotics platforms, and sensor systems that require on‑device AI inference with stringent power and thermal budgets.
Features
- In‑memory analog compute using memristor‑based non‑volatile memory neurons, removing digital data shuttling
- Ultra‑low‑power operation with ~1000× lower energy use than comparable digital AI accelerators
- Support for diverse neural architectures, including convolutional and recurrent networks, scalable to millions of neurons
- Hardware‑aware training and simulation platform (digital twins) for process‑voltage‑temperature (PVT) mitigation
- Integrated digital microcontroller for calibration, interface management, and programmable control
- Flexible deployment options ranging from chip IP to packaged modules and full system solutions