IROC Technologies provides Electronic Design Automation (EDA) tools and services for soft error rate (SER) analysis and mitigation. Their solutions enable semiconductor designers to simulate and analyze radiation effects at the transistor, circuit, and system levels, enhancing the reliability of complex SoCs.
Funding
$5M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
Semiconductor devices are increasingly vulnerable to soft errors caused by radiation particles, which can lead to critical system failures. Accurately predicting and mitigating these effects at the transistor, circuit, and system levels is essential for ensuring functional reliability, especially in safety-critical applications.
Solution
IROC Technologies provides a comprehensive suite of Electronic Design Automation (EDA) tools and services for soft error rate (SER) analysis and mitigation. Their solutions enable designers to simulate and analyze fault propagation at the cell and circuit levels, as well as perform system-level assessments. Complementing their software offerings, IROC Technologies also provides radiation effects testing and expert consulting services. This integrated approach helps customers enhance the reliability of their complex Systems-on-Chip (SoCs) and meet stringent functional safety requirements.
Target Audience
The primary target audience includes semiconductor design engineers, reliability engineers, and functional safety managers in industries such as automotive, aerospace, medical, and high-performance computing that require high levels of functional reliability.
Features
- **TFIT (Transistor Failure In Time):** A transistor-level soft error simulator that provides high-speed, accurate simulation of radiation effects for standard cells and custom designs across various process nodes (down to 3nm). It leverages foundry-provided characterization models and proprietary algorithms for SPICE-level simulations up to 100x faster than TCAD.
- **SoCFIT:** A System-on-Chip (SoC) level soft error analysis and mitigation tool that assesses fault propagation and its impact on system reliability. It supports RTL or gate-level netlists and can incorporate timing information (SDF files) to evaluate fault masking mechanisms, including sequential, combinational, and memory masking.
- **SERTEST:** A service offering for radiation effects measurement and testing, including high-energy neutrons, thermal neutrons, protons, and heavy ions. It also provides in-house Co60 TID and alpha particle testing, fault injection, and alpha emissivity measurements, adhering to JEDEC JESD standards and MIL/ESA methods.
- **SERPRO:** Consulting services focused on soft error rate management and mitigation strategies. This includes identification of system vulnerabilities, assessment of error rates and failure modes, and the application of simulation tools for accurate SER calculations.
- **Siemens EDA Integration:** TFIT is integrated into the Siemens Calibre LVS flow, enabling seamless transistor data extraction and accelerated radiation effects analysis.
- **Foundry Support:** Availability of foundry-approved TFIT models for major process nodes from TSMC, Samsung, GlobalFoundries, and STM.