Inspirit IoT offers Xcelo™, a chip-agnostic high-level synthesis tool for FPGAs that enhances design productivity by up to five times compared to traditional RTL methods. The platform integrates machine-learning IPs and provides accurate performance modeling, enabling efficient design space exploration for cloud, server, and edge devices.
Funding
$909.7K raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
Designing hardware for FPGAs using traditional Register Transfer Level (RTL) methods is a time-consuming and complex process, hindering design productivity and slowing down the development cycle for cloud, server, and edge devices. Existing High-Level Synthesis (HLS) tools often rely on pragmas, limiting out-of-the-box Quality of Results (QoR).
Solution
Inspirit IoT's Xcelo™ is a chip-agnostic High-Level Synthesis (HLS) tool for FPGAs that significantly enhances design productivity. Xcelo™ leverages advanced LLVM IR and incorporates machine-learning IPs to streamline the hardware design process. The tool provides an accurate high-level area/performance model, enabling efficient Design Space Exploration (DSE) and optimized hardware implementations. By employing pipelined IPs, advanced loop optimizations, and polyhedral model-based optimizations, Xcelo™ delivers superior performance compared to traditional RTL designs.
Target Audience
The primary target audience includes hardware design engineers and teams working on FPGA-based solutions for cloud, server, and edge computing applications.
Features
- Chip-agnostic HLS tool compatible with various FPGA architectures
- Machine-learning IPs and seamless IP integration capabilities
- Accurate high-level area/performance modeling for efficient Design Space Exploration
- Pipelined IPs and advanced loop optimizations for enhanced performance
- Polyhedral model-based optimizations for improved resource utilization
- Multi-cycle path constraints support for timing closure
- Leverages advanced LLVM IR for efficient code generation
- Higher out-of-the-box Quality of Results (QoR) without relying on pragmas