Inspire Semiconductor provides the Thunderbird accelerated computing platform, a "supercomputer-cluster-on-a-chip" solution for HPC and AI workloads. Its RISC-V architecture and all-CPU programming model offer energy efficiency and simplified development, reducing datacenter TCO and carbon footprint.
Funding
$3M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
Founders
Product
Problem
Existing High-Performance Computing (HPC) and AI acceleration solutions are often expensive, difficult to program, power-intensive, and limited in their application scope. This creates significant barriers for organizations seeking to maximize computational performance and efficiency.
Solution
Inspire Semiconductor offers the Thunderbird accelerated computing platform, designed to provide a versatile and energy-efficient alternative for HPC and AI workloads. This platform leverages a "supercomputer-cluster-on-a-chip" architecture featuring thousands of RISC-V CPU cores. The open-standard RISC-V ISA and a developer-friendly all-CPU programming model simplify software development and eliminate vendor lock-in, enabling the integration of HPC and AI tasks on a single platform. Its high-speed mesh network fabric ensures efficient inter-core communication, addressing bottlenecks in applications requiring extensive thread cooperation. This approach delivers substantial datacenter total cost of ownership savings and reduced carbon footprint compared to traditional GPU-based systems.
Target Audience
The primary target audience includes organizations in sectors such as financial services, computer-aided engineering, energy, climate modeling, and life sciences & drug discovery that require high-performance, energy-efficient computing solutions.
Features
- Thunderbird "supercomputer cluster-on-a-chip" architecture with thousands of 64-bit RISC-V superscalar CPU cores.
- High-speed mesh network fabric for extreme bandwidth and low-latency inter- and intra-chip communications, supporting arrays of up to 256 chips.
- Developer-friendly, all-CPU programming model compatible with the established RISC-V software ecosystem, simplifying development and maintenance.
- Optimized for High-Performance Computing (HPC), AI/machine learning, and graph analytics workloads.
- High energy efficiency, delivering 75 GFLOPS/Watt (FP64).
- Deterministic and predictable performance, suitable for real-time and safety-critical applications.
- Support for onboard LPDDR memory, NVMe storage, PCIe, and 10Gb Ethernet.
- Dedicated acceleration for specific cryptography algorithms.
- Potential for significant datacenter TCO savings through reduced real estate, power, and cooling requirements.