InfiniNode Technologies provides high‑performance, energy‑efficient interconnect IP for heterogeneous and multi‑chiplet SoCs. Its modular fabric offers coherent and non‑coherent options with an integrated system‑level cache, delivering near‑wire‑propagation latency and low power per bit while supporting standard protocols such as AXI, OCP, and TileLink. The IP integrates into existing RTL flows, reducing validation effort and accelerating SoC development for semiconductor and ASIC designers.
Funding
$5.6M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
CVNEPHTCFounders
Product
Problem
Designers of heterogeneous and multi-chiplet System-on-Chip (SoC) architectures encounter escalating interconnect latency and bandwidth bottlenecks as core counts grow. Conventional bus and router implementations add hop and protocol overhead that pushes real latency far above the physical limit set by wire propagation. This latency penalty reduces overall performance and increases energy consumption, hindering rapid time‑to‑market for advanced silicon products.
Solution
InfiniNode Technologies delivers a portfolio of high‑performance, energy‑efficient system IP blocks that replace legacy interconnects with a coherent and non‑coherent fabric optimized for near‑physical‑limit latency. The fabric incorporates a system‑level cache that enables low‑latency data sharing across cores and chiplets, preserving bandwidth while minimizing power draw. Its modular architecture allows designers to select only the required features, ensuring seamless scaling as core counts and network size increase. By integrating the IP directly into the SoC design flow, InfiniNode reduces validation effort and accelerates development cycles for next‑generation heterogeneous chips. The solution also supports standard industry interfaces and verification suites, facilitating straightforward integration into existing design ecosystems.
Target Audience
Primary customers are semiconductor companies, ASIC design houses, and in‑house SoC engineering teams developing heterogeneous or multi‑chiplet processors that require high‑bandwidth, low‑latency interconnect solutions.
Features
- Coherent interconnect fabric with integrated system‑level cache for low‑latency data coherence across multi‑chiplet domains
- Non‑coherent high‑throughput fabric option for latency‑insensitive workloads
- Ultra‑low latency path design that approaches the theoretical wire‑propagation limit
- Energy‑efficient routing logic and power‑gating mechanisms to minimize dynamic power per bit transferred
- Fully modular IP blocks with configurable parameters (port count, topology, QoS policies) for custom SoC architectures
- Support for industry‑standard protocols (AXI, OCP, TileLink) and verification IP suites
- Scalable topology that maintains performance as core count and bandwidth demands grow
- Compatibility with standard EDA tools and RTL integration flows for rapid design closure