IC Bench provides an AI‑agent platform that automates design‑rule checks, layout optimization, synthesis and verification within existing EDA toolchains. The agents learn from historical design data and expose a unified REST/GraphQL API for seamless integration with Cadence, Synopsys and Mentor tools, while a web dashboard delivers real‑time metrics and corrective recommendations. The solution supports on‑premise and secure cloud deployments for ASIC and FPGA design teams.
Funding
Funding not disclosed
Founders
Product
Problem
Electronic Design Automation (EDA) workflows are heavily manual, requiring extensive rule definition, iterative simulation, and coordination across fragmented toolchains, which prolongs design cycles and increases the likelihood of errors. Scaling designs for advanced process nodes further amplifies the need for expert intervention and time‑consuming verification steps.
Solution
IC Bench delivers an AI‑agent platform that embeds intelligent automation directly into existing EDA environments. The agents ingest historical design data to automatically generate design‑rule checks, propose layout optimizations, and drive synthesis and verification tasks without manual scripting. A unified API orchestrates multiple EDA tools, eliminating context‑switching and reducing the overhead of custom integration. Continuous learning updates the agents’ models after each run, improving prediction accuracy and decreasing rework. A web‑based dashboard visualizes key performance metrics, risk indicators, and actionable recommendations for designers. The solution is compatible with leading EDA suites (Cadence, Synopsys, Mentor) and supports both on‑premise and cloud deployments, allowing teams to accelerate time‑to‑market while preserving data security.
Target Audience
Primary users are ASIC and FPGA design engineers at fabless semiconductor companies, as well as EDA tool integrators and R&D groups seeking to automate and accelerate their design workflows.
Features
- AI agents that automatically generate and execute design‑rule checks based on prior design patterns
- Machine‑learning‑driven layout and placement optimization suggestions to improve performance and area utilization
- Automated synthesis and verification pipelines that reduce manual script maintenance
- Unified REST/GraphQL API for seamless integration with existing EDA toolchains and custom workflows
- Continuous model retraining from each design iteration to enhance accuracy over time
- Web dashboard with real‑time metrics, risk heatmaps, and recommended corrective actions
- Compatibility layer for major EDA platforms (Cadence Virtuoso, Synopsys Design Compiler, Mentor Calibre)
- Deployable on‑premise or via secure cloud infrastructure with role‑based access controls