Current computational hardware architectures face limitations in achieving the theoretical maximum speed and energy efficiency required for advanced AI applications. This bottleneck hinders the development of systems capable of handling increasingly complex computational demands.

Great Sky is developing a novel hardware architecture that integrates photonics, superconductors, and semiconductors to overcome existing computational limitations. This approach leverages the unique properties of each technology to create a new class of compute designed for high-performance applications. Superconductors provide unparalleled speed and energy efficiency for core computations, while photonics enables high-bandwidth, low-latency communication between processing elements, mimicking neural connectivity. Semiconductors serve as the integration layer, facilitating control logic and interfacing between photonic and superconducting components. This monolithic platform aims to deliver intelligence at the physical limits of speed and efficiency.

Integrated Photonics: Utilizes multi-planar photonic waveguides on wafers and fiber coupling for high-density, low-latency inter-component communication, addressing communication bottlenecks in conventional neural networks.

Superconducting Components: Employs superconducting devices, such as Josephson junctions and superconducting single-photon detectors, for ultra-fast and energy-efficient computation and signal detection.

Semiconductor Integration: Leverages silicon for control logic, amplification, light emission (LEDs), and interfacing between superconducting and photonic elements.

Superconducting Loop Neuron Concept: Based on a published concept for a superconducting loop neuron, forming the foundational element of the architecture.

hTrons for Interfacing: Implemented superconducting impedance converters (hTrons) to enable seamless interfacing between low-voltage superconducting circuits and semiconductor components.

Single-Photon Synapses: Developed superconducting optoelectronic single-photon synapses capable of responding to high presynaptic spike rates (>10 MHz) with extremely low dynamic power consumption (33 aJ per synapse event).

Programmable Memory Cells: Integrated memory cells with superconducting nanowire single-photon detectors and Josephson junctions, offering high internal state capacity (over 400 states) and low programming energies (0.4 fJ including cooling power).

Phenomenological Modeling: Developed a mathematical framework that significantly accelerates simulation speeds (factor of ten thousand) while maintaining accuracy, enabling efficient modeling of full networks and neuromorphic algorithm experimentation.

The primary customers are organizations and researchers developing demanding computational applications, particularly in the field of artificial intelligence and machine learning, who require hardware operating at the theoretical limits of speed and efficiency.