Gemesys builds a neuromorphic processor that uses event‑driven spiking neural networks and hybrid analog‑digital compute units to deliver high‑throughput, low‑power AI inference and training. The chip’s massive on‑chip parallelism and built‑in learning reduce data movement and energy per operation, offering a scalable hardware accelerator for data‑center, edge, and embedded AI systems.
Funding
$9.1M raised to dateRaised to date based on public sources. This may differ from the amount the company actually raised and is based only on what is publicly available on the internet.
4OAVALFounders
Product
Problem
Current AI workloads are constrained by the limits of conventional von Neumann processors, leading to high power consumption, latency, and scaling challenges for increasingly complex models. These computing bottlenecks hinder the deployment of AI across data‑center, edge, and embedded environments.
Solution
Gemesys develops a neuromorphic processor that mimics key principles of the human brain to deliver high‑throughput, low‑power computation for AI workloads. The architecture leverages event‑driven processing, massive parallelism, and on‑chip learning to execute deep‑learning inference and training more efficiently than traditional GPUs or ASICs. By integrating analog/digital hybrid circuits, the chip reduces data movement and energy per operation, enabling scalable AI performance for both cloud‑scale and edge devices. Gemesys offers a hardware platform that can be integrated into existing AI systems, providing developers with a path to accelerate models while lowering operational costs.
Target Audience
Primary customers are AI hardware integrators, data‑center operators, and edge‑device manufacturers seeking energy‑efficient acceleration for deep‑learning models.
Features
- Neuromorphic architecture with spiking neural network support for event‑driven processing
- Hybrid analog‑digital compute units that minimize data transfer and improve energy efficiency
- Massive on‑chip parallelism enabling high throughput for inference and training
- Built‑in on‑chip learning capabilities for continual adaptation at the edge
- Scalable design compatible with standard PCB form factors and existing AI system interfaces