Fluid Silicon
Fluid Silicon provides a customizable platform for FPGA adaptation and resilience, measuring timing slack on individual logic elements in-system at operating speed to keep each device within its measured margin. The platform supports AMD and Altera devices, requires no RTL changes, and is deployed on-premises, with a full-chip sweep taking about one second and per-link precision under 20 ps.
- Semiconductor
- Data & Analytics
- Software Only
Funding
Founders
Founder details are not available yet.
Product
Problem
FPGA fleets run chips with timing margins set for the statistical worst-case die at end of life, even though most chips carry 30-54% excess margin at realistic utilization. This one-size-fits-all approach wastes energy, leaves performance on the table, and provides no visibility into which logic elements are degrading—leading to surprise failures, unplanned downtime, and maintenance scheduled around guesses.
Solution
Fluid Silicon adds a small health layer beside an existing FPGA design that measures timing slack on individual logic elements—LUTs, carry blocks, and the links between them—at operating speed, with a full sweep taking about one second and each link resolved to under 20 ps. The platform fits an aging curve to each card's own temperature history, projects time-to-threshold per element, and presents a fleet-wide health view. Monitoring and modeling are read-only; optional tuning adjusts voltage and frequency to what each chip can sustain, and repair moves only a degrading path to a healthy resource through the customer's change process. Every change is re-measured, keeping the margin at measurement error plus drift rather than worst-case population bounds. The platform runs on-premises, requires no RTL changes, and uses a vendor-neutral telemetry schema across AMD and Altera devices.
Target Audience
Primary customers are data-center operators and enterprises running large FPGA fleets (hundreds to thousands of cards) across AMD and Altera families, as well as aerospace and defense programs deploying FPGAs at the edge where surprises are expensive and maintenance windows are constrained.
Features
- Per-element timing slack measurement on LUTs, carry blocks, and links, resolved to under 20 ps with a full-chip sweep in about one second
- Aging model fitted to each card's temperature history, producing time-to-threshold predictions per element and per card
- Fleet dashboard showing median slack, weakest element per card, and actionable watch lists across mixed AMD and Altera families
- Low overhead: under 1% of LUTs and under 5% of flip-flops on a production shell, under 2% delay impact, no RTL changes, no JTAG exposure
- On-site deployment with vendor-neutral telemetry schema and alert thresholds; monitoring feeds the model and tuning, and every change is re-measured
- Edge-capable operation for aerospace and defense, scaling voltage within measured margin on platforms without fleet server access
- Device support from 28 nm to 10 nm class, with AMD 7-series, UltraScale, and UltraScale+ supported today; Altera Agilex 7 select devices supported, with Stratix 10/Arria 10 and AMD Versal AI Core in development
- Characterization at incoming, monitoring in production, and characterization again at exit, providing per-card evidence for resale, reuse, or retirement