Funding
Funding not disclosed
Founders
Product
Problem
Modern computing systems face increasing demands for higher performance and memory capacity, while simultaneously requiring reduced energy consumption and low latency. Traditional memory architectures struggle to balance these competing demands, leading to inefficiencies and limitations in various applications.
Solution
FLC Technology Group offers a memory architecture solution that addresses these challenges by utilizing a final-level cache (FLC) system. This architecture employs a combination of high-bandwidth DRAM as a cache and less expensive flash memory or SSDs for main memory. By intelligently managing data placement and leveraging a massive cache architecture with a high hit rate, FLC technology reduces power dissipation, lowers access latency, and provides virtually unlimited memory capacity. The FLC architecture can be applied to low-end systems like smartphones and laptops, high-end systems, and generative AI servers, improving overall system efficiency and performance.
Target Audience
The primary target audience includes manufacturers of smartphones, laptops, automotive systems, and servers, as well as data centers and other organizations seeking to improve the performance and efficiency of their computing infrastructure.
Features
- High-bandwidth DRAM as final-level cache (FLC) to enhance the performance of standard DDR memory
- DDR memory can be used as a massive workload cache to hide the latency of storage (e.g., SSD) when used as a final memory
- Greater than 95% cache hit rate for FLC-1 high bandwidth cache
- Fully-associative look-up engine with large entries (e.g., 32K/64K for 128MB cache)
- Large cache line (e.g., 2KB, 4KB, 16KB, or larger)
- Multi-level caching
- Chiplet-based design for modularity and flexibility