EvoChip provides the AltiCore framework, a patented logic‑dominant architecture that replaces arithmetic‑heavy neural compute with trained operator chains, delivering orders‑of‑magnitude efficiency gains while preserving model accuracy. Its ecosystem includes deterministic AI inference for microcontrollers (AltiCoreMCU), high‑performance CPU runtimes (AltiCoreSWP), and FPGA/ASIC pipelines (AltiCoreHDL) that enable AI deployment from 8‑bit edge devices to custom silicon capable of billions of inferences per second.
Funding
Funding not disclosed
Founders
Product
Problem
Conventional neural networks rely on dense matrix multiplication, leading to high arithmetic intensity, excessive power consumption, and large memory requirements. This makes scaling AI costly and prevents deployment on resource‑constrained edge devices such as microcontrollers, while data‑center hardware faces “dark silicon” limits.
Solution
EvoChip’s patented AltiCore framework replaces arithmetic‑heavy neural compute with trained, logic‑dominant operator chains. By minimizing numeric operations, AltiCore delivers orders‑of‑magnitude efficiency gains while preserving model accuracy. The ecosystem provides software runtimes for CPUs, deterministic inference and optional on‑device training for microcontrollers, and FPGA/ASIC pipelines that achieve one inference per clock cycle with deterministic latency. This unified approach enables AI to run locally on 8‑bit MCUs, accelerates workloads on standard servers, and scales to custom silicon capable of billions of inferences per second.
Target Audience
Primary customers are embedded system developers and OEMs building AI‑enabled products for edge devices, as well as hardware architects and data‑center operators seeking high‑throughput, low‑power AI acceleration on CPUs, FPGAs, or custom ASICs.
Features
- AltiCoreMCU: deterministic AI inference on microcontrollers with static memory footprints as low as 521 bytes and optional on‑device training, achieving ~9 k inferences / s on a 16 MHz MCU.
- AltiCoreSWP: high‑performance CPU runtime that restructures models into logic‑dominant chains, delivering 13‑41× speedups over state‑of‑the‑art NN CPU implementations while matching accuracy.
- AltiCoreHDL: FPGA/ASIC implementation that maps AltiCore models to fixed‑depth synchronous pipelines, providing 1 inference per clock per core, cycle‑constant latency, and up to 3.19 billion inferences / s in a 17‑core FPGA demo.
- Logic‑dominant architecture: reduces arithmetic intensity, eliminating the need for external DRAM and NPU accelerators, and enabling deterministic, power‑efficient execution.
- Patented mathematical foundation: a new framework that replaces dense matrix multiplication with minimal‑overhead operator chains, applicable across all compute tiers.
- Standardized token interface for seamless integration with existing software stacks and hardware design flows.