Thinktrans Semiconductor (Wuhan) Co., Ltd provides high‑density packaging substrates for integrated circuits using its proprietary ion‑implantation vapor deposition (IVD) and ion‑implantation semi‑additive process (IVD SAP) technologies. These processes enable finer line widths and tighter spacing than traditional copper plating, supporting multi‑layer CSP, FC‑CSP, FC‑BGA, and carrier board applications for memory, mobile, and display chips. The company manufactures these substrates at a large‑scale Wuhan facility, delivering reliable, high‑precision solutions to fabless and IC manufacturers.
Funding
Funding not disclosed
Founders
Product
Problem
Manufacturers of integrated circuits face constraints in substrate technology, such as limited line width/spacing and reliance on traditional copper plating processes, which hinder the production of high‑density, high‑performance chips for memory, mobile, and display applications.
Solution
Thinktrans Semiconductor offers advanced packaging substrates that leverage proprietary ion‑implantation vapor deposition (IVD) and ion‑implantation semi‑additive process (IVD SAP) technologies. By injecting metal ions directly onto substrate surfaces, these processes achieve finer line widths and tighter spacing than conventional chemical plating, enabling multi‑layer carrier boards for CSP, FC‑CSP, FC‑BGA, and ROS applications. The resulting substrates support high‑density interconnects, reduced parasitic resistance, and improved thermal performance, meeting the demands of memory chips, smartphones, TVs, and other primary ICs. Thinktrans manufactures these substrates at its large‑scale facility in Wuhan, providing customers with reliable, high‑precision solutions for next‑generation semiconductor devices.
Target Audience
Primary customers are semiconductor fabless companies and integrated circuit manufacturers requiring high‑density packaging substrates for memory, mobile, and display chip products.
Features
- Ion Implantation Vapor Deposition (IVD) metallization delivering line widths as low as 15 µm with superior uniformity
- Ion Implantation Semi‑Additive Process (IVD SAP) enhancing traditional SAP with finer feature control and reduced process steps
- Multi‑layer substrate offerings: CSP (2–6 layers), FC‑CSP (2–6 layers, 80–280 µm thickness), FC‑BGA (8–22 layers, ultra‑fine line/spacing)
- Carrier boards (ROS) with customizable area (e.g., 50 × 50 mm) and ultra‑low line widths for high‑frequency and high‑density applications
- High‑volume production capacity on a 150‑acre campus with integrated process flow for consistent quality and yield